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this document contains information on a product under development at spansion, llc. the information is intended to help you eva luate this product. do not design in this product without contacting the factory. spansion reserves the right to change or discontinue work on this proposed product without notice. publication number S71GS256/128n_00 revision a amendment 0 issue date december 17, 2004 advance information S71GS256/128n based mcps stacked multi-chip product (mcp) 256/128 megabit (16/8m x 16-bit) cmos 3.0 volt v cc and 1.8 v v io mirrorbit tm uniform sector page-mode flash memory with 64/32 megabit (4/2m x 16-bit) 1.8v psram data sheet distinctive characteristics mcp features power supply voltage ?flash memory v cc : 2.7v to 3.1v v io : 1.65v to 1.95v ? psram v cc : 1.7 v to 1.95 v high performance 110 ns access time 30 ns page read times packages: ? 8.0x11.6x1.2 mm fbga (tla084) operating temperature ? -25c to +85c (wireless) general description the s71gs series is a product line of stacked multi-chip product (mcp) packages and consists of one s29gl flash memory die with 1.8 v v io one 1.8 v psram (note) note: burst mode features of the psram in the s71gs family of mcps is not avail- able. this mcp uses the page mode operation which utilizes the page mode flash and page mode feature-set of the psram.
2 S71GS256/128n based mcps S71GS256/128n_00_a0 december 17, 2004 advance information product selector guide part number S71GS256nc0 speed/voltage option full voltage range v cc = 2.7 v to 3.1 v (flash) v io = 1.65 v to 1.95 v (flash) v cc = 1.7 v to 1.95 v (psram) flash psram max. access time (ns) 110 70 max. ce# access time (ns) 110 70 max. page access time (tpacc) 30 25 max. oe# access time (ns) 30 25 part number s71gs128nb0 speed/voltage option full voltage range v cc = 2.7 v to 3.1 v (flash) v io = 1.65 v to 1.95 v (flash) v cc = 1.7 v to 1.95 v (psram) flash psram max. access time (ns) 110 70 max. ce# access time (ns) 110 70 max. page access time (tpacc) 30 25 max. oe# access time (ns) 30 25
december 17, 2004 S71GS256/128n_00_a0 3 advance information S71GS256/128n based mcps general description . . . . . . . . . . . . . . . . . . . . . . . . 1 product selector guide . . . . . . . . . . . . . . . . . . . . . 2 mcp block diagrams . . . . . . . . . . . . . . . . . . . . . . . 7 connection diagrams . . . . . . . . . . . . . . . . . . . . . . 9 input/output descriptions . . . . . . . . . . . . . . . . . . . 11 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ordering information . . . . . . . . . . . . . . . . . . . . . . . 13 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . 15 s29glxxxn mirrorbit tm flash family general description . . . . . . . . . . . . . . . . . . . . . . . 17 product selector guide . . . . . . . . . . . . . . . . . . . . . 19 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 s29gl512n ....................................................................................................... 22 s29gl256n ...................................................................................................... 22 s29gl128n ...................................................................................................... 22 device bus operations . . . . . . . . . . . . . . . . . . . . . . 23 table 1. device bus operations ........................................... 23 versatileio tm (v io ) control .............................................................................23 requirements for reading array data .........................................................23 page mode read ............................................................................................. 24 writing commands/command sequences ................................................ 24 write buffer .................................................................................................... 24 accelerated program operation .............................................................. 24 autoselect functions .....................................................................................25 standby mode .......................................................................................................25 automatic sleep mode ......................................................................................25 reset#: hardware reset pin .........................................................................25 output disable mode ....................................................................................... 26 table 2. sector address table?s29gl512n ........................... 26 table 3. sector address table?s29gl256n ........................... 41 table 4. sector address table?s29gl128n ........................... 48 autoselect mode .................................................................................................52 table 5. autoselect codes, (high voltage method) ................ 53 sector protection ................................................................................................53 persistent sector protection .......................................................................53 password sector protection ........................................................................53 wp# hardware protection .........................................................................53 selecting a sector protection mode .........................................................53 advanced sector protection ...........................................................................54 lock register ........................................................................................................54 table 6. lock register ........................................................ 55 persistent sector protection ...........................................................................55 dynamic protection bit (dyb) ...................................................................55 persistent protection bit (ppb) ..................................................................56 persistent protection bit lock (ppb lock bit) ......................................56 table 7. sector protection schemes ..................................... 57 persistent protection mode lock bit ...........................................................57 password sector protection ........................................................................... 58 password and password protection mode lock bit ............................... 58 64-bit password ...................................................................................................59 persistent protection bit lock (ppb lock bit) ...........................................59 secured silicon sector flash memory region ............................................59 write protect (wp#) ........................................................................................ 61 hardware data protection .............................................................................. 61 low vcc write inhibit ................................................................................ 61 write pulse ?glitch? protection ................................................................ 61 logical inhibit .................................................................................................... 61 power-up write inhibit ................................................................................ 61 common flash memory interface (cfi) . . . . . . . 61 table 8. cfi query identification string ................................ 62 table 9. system interface string.......................................... 63 table 10. device geometry definition ................................... 64 table 11. primary vendor-specific extended query ................ 65 command definitions . . . . . . . . . . . . . . . . . . . . . . 65 reading array data ........................................................................................... 66 reset command ................................................................................................. 66 autoselect command sequence ................................................................... 66 enter secured silicon sector/exit secured silicon sector command sequence ............................................................................ 67 word program command sequence .......................................................... 67 unlock bypass command sequence ........................................................68 write buffer programming .........................................................................68 accelerated program .................................................................................... 69 figure 1. write buffer programming operation....................... 70 figure 2. program operation ............................................... 71 program suspend/program resume command sequence ..................... 71 figure 3. program suspend/program resume ........................ 72 chip erase command sequence ................................................................... 72 sector erase command sequence .................................................................73 figure 4. erase operation ................................................... 74 erase suspend/erase resume commands .................................................. 74 lock register command set definitions .................................................... 75 password protection command set definitions ...................................... 75 non-volatile sector protection command set definitions .................. 77 global volatile sector protection freeze command set ...................... 77 volatile sector protection command set .................................................. 78 secured silicon sector entry command ..................................................... 79 secured silicon sector exit command ........................................................ 79 command definitions ....................................................................................... 80 table 12. s29gl512n, s29gl256n, s29gl128n command definitions, x16 ................................................................. 80 write operation status ................................................................................... 83 dq7: data# polling ........................................................................................... 83 figure 5. data# polling algorithm ........................................ 84 ry/by#: ready/busy# .......................................................................................84 dq6: toggle bit i ............................................................................................... 85 figure 6. toggle bit algorithm ............................................. 86 dq2: toggle bit ii ..............................................................................................86 reading toggle bits dq6/dq2 ..................................................................... 87 dq5: exceeded timing limits ........................................................................ 87 dq3: sector erase timer ................................................................................ 87 dq1: write-to-buffer abort ...........................................................................88 table 13. write operation status ......................................... 88 absolute maximum ratings . . . . . . . . . . . . . . . . 89 figure 7. .......................................................................... 89 figure 8. maximum positive overshoot waveform.......................................................... 89 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . 89 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 90 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 figure 9. test setup........................................................... 91 table 14. test specifications ............................................... 91 key to switching waveforms . . . . . . . . . . . . . . . . 91 figure 10. input waveforms and measurement levels ............ 91 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 92
4 S71GS256/128n_00_a0 december 17, 2004 advance information read-only operations?s29gl128n, s29gl256n, s29gl512n .......... 92 figure 11. read operation timings ....................................... 93 figure 12. page read timings .............................................. 93 hardware reset (reset#) .............................................................................. 94 figure 13. reset timings..................................................... 94 erase and program operations?s29gl128n, s29gl256n, s29gl512n ...................................................................................95 figure 14. program operation timings .................................. 96 figure 15. accelerated program timing diagram .................... 96 figure 16. chip/sector erase operation timings ..................... 97 figure 17. data# polling timings (during embedded algorithms) ............................................ 98 figure 18. toggle bit timings (during embedded algorithms) .. 99 figure 19. dq2 vs. dq6 ...................................................... 99 alternate ce# controlled erase and program operations- s29gl128n, s29gl256n, s29gl512n ........................................................100 figure 20. alternate ce# controlled write (erase/ program) operation timings .............................................. 101 erase and programming performance . . . . . . 102 tsop pin and bga package capacitance . . . . 102 cellularram type 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 general description . . . . . . . . . . . . . . . . . . . . . . 103 figure 21. functional block diagram ................................... 104 table 15. signal descriptions .............................................105 table 16. bus operations?asynchronous mode ....................106 table 17. bus operations?burst mode ................................107 functional description . . . . . . . . . . . . . . . . . . . . 107 power-up initialization .................................................................................... 107 figure 22. power-up initialization timing............................. 108 bus operating modes . . . . . . . . . . . . . . . . . . . . . 108 asynchronous mode ........................................................................................108 figure 23. read operation (adv# low) ............................. 108 figure 24. write operation (adv# low) ........................... 109 page mode read operation ........................................................................109 figure 25. page mode read operation (adv# low) ............. 110 burst mode operation .....................................................................................110 figure 26. burst mode read (4-word burst) ........................ 111 figure 27. burst mode write (4-word burst) ....................... 111 mixed-mode operation ................................................................................... 112 wait operation ............................................................................................... 112 figure 28. wired or wait configuration .............................. 112 lb#/ub# operation .......................................................................................... 113 figure 29. refresh collision during read operation.............. 113 figure 30. refresh collision during write operation ............ 114 low-power operation . . . . . . . . . . . . . . . . . . . . . 114 standby mode operation ................................................................................ 114 temperature compensated refresh ........................................................... 114 partial array refresh ........................................................................................ 115 deep power-down operation ...................................................................... 115 configuration registers . . . . . . . . . . . . . . . . . . . . 115 access using cre .............................................................................................. 115 figure 31. configuration register write, asynchronous mode fol- lowed by read ................................................................ 116 figure 32. configuration register write, synchronous mode fol- lowed by read0............................................................... 117 bus configuration register ............................................................................. 117 table 18. bus configuration register definition ....................118 table 19. sequence and burst length .................................119 burst length (bcr[2:0]): default = continuous burst ...................... 119 burst wrap (bcr[3]): default = no wrap .......................................... 119 output impedance (bcr[5:4]): default = outputs use full drive strength ............................................................................................................120 table 20. output impedance ............................................. 120 wait configuration (bcr[8]): default = wait transitions one clock before data valid/invalid ...............................................................120 wait polarity (bcr[10]): default = wait active high ...............120 figure 33. wait configuration (bcr[8] = 0) ....................... 120 figure 34. wait configuration (bcr[8] = 1) ....................... 121 figure 35. wait configuration during burst operation.......... 121 latency counter (bcr[13:11]): default = three-clock latency ......121 table 21. variable latency configuration codes ................... 121 figure 36. latency counter (variable initial latency, no refresh collision) ........................................................................ 122 operating mode (bcr[15]): default = asynchronous operation .122 refresh configuration register .....................................................................122 table 22. refresh configuration register mapping ................ 123 partial array refresh (rcr[2:0]): default = full array refresh .... 123 table 23. 128mb address patterns for par (rcr[4] = 1) ....... 123 table 24. 64mb address patterns for par (rcr[4] = 1) ........ 124 table 25. 32mb address patterns for par (rcr[4] = 1) ........ 124 deep power-down (rcr[4]): default = dpd disabled ..................124 temperature compensated refresh (rcr[6:5]): default = +85oc op- eration ..............................................................................................................124 page mode operation (rcr[7]): default = disabled ........................124 absolute maximum ratings . . . . . . . . . . . . . . . . 125 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . 126 table 26. electrical characteristics and operating conditions . 126 table 27. temperature compensated refresh specifications and conditions ....................................................................... 127 table 28. partial array refresh specifications and conditions . 127 table 29. deep power-down specifications .......................... 127 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . 128 figure 37. ac input/output reference waveform................. 128 figure 38. output load circuit ........................................... 128 table 30. output load circuit ............................................ 128 table 31. asynchronous read cycle timing requirements .... 129 table 32. burst read cycle timing requirements ................ 130 table 33. asynchronous write cycle timing requirements ... 131 table 34. burst write cycle timing requirements ............... 131 timing diagrams ................................................................................................ 132 figure 39. initialization period ........................................... 132 table 35. initialization timing parameters ........................... 132 figure 40. asynchronous read .......................................... 133 table 36. asynchronous read timing parameters ................ 133 figure 41. asynchronous read using adv# ........................ 135 table 37. asynchronous read timing parameters using adv# 135 figure 42. page mode read .............................................. 137 table 38. asynchronous read timing parameters?page mode operation ....................................................................... 137 figure 43. single-access burst read operation?variable latency .......................................................................... 139 table 39. burst read timing parameters?single access, variable latency .......................................................................... 139 figure 44. four-word burst read operation?variable latency 141 table 40. burst read timing parameters?4-word burst ....... 142 figure 45. four-word burst read operation (with lb#/ub#). 143 table 41. burst read timing parameters?4-word burst with lb#/ ub# ............................................................................... 144 figure 46. read burst suspend ......................................... 145 table 42. burst read timing parameters?burst suspend ..... 145 figure 47. continuous burst read showing an output delay with bcr[8] = 0 for end-of-row condition ................................. 146 table 43. burst read timing parameters?bcr[8] = 0 ......... 146 figure 48. ce#-controlled asynchronous write .................. 147
december 17, 2004 S71GS256/128n_00_a0 5 advance information table 44. asynchronous write timing parameters?ce#-controlled .............................................147 figure 49. lb#/ub#-controlled asynchronous write ........... 149 table 45. asynchronous write timing parameters?lb#/ub#- controlled .......................................................................149 figure 50. we#-controlled asynchronous write.................. 151 table 46. asynchronous write timing parameters?we#- controlled .......................................................................151 figure 51. asynchronous write using adv#....................... 153 table 47. asynchronous write timing parameters using adv# ....................................................154 figure 52. burst write operation ...................................... 155 table 48. burst write timing parameters ...........................156 figure 53. continuous burst write showing an output delay with bcr[8] = 0 for end-of-row condition ................................. 157 table 49. burst write timing parameters?bcr[8] = 0 ........157 figure 54. burst write followed by burst read .................. 158 table 50. write timing parameters?burst write followed by burst read .....................................................................158 table 51. read timing parameters?burst write followed by burst read ..............................................................................158 figure 55. asynchronous write followed by burst read ...... 159 table 52. write timing parameters?asynchronous write followed by burst read ....................................................160 table 53. read timing parameters?asynchronous write followed by burst read .................................................................160 figure 56. asynchronous write (adv# low) followed by burst read.............................................................................. 161 table 54. asynchronous write timing parameters?adv# low ...................................................161 table 55. burst read timing parameters ............................162 figure 57. burst read followed by asynchronous write (we#-con- trolled) ........................................................................... 163 table 56. burst read timing parameters ............................164 table 57. asynchronous write timing parameters?we# controlled .............................................164 figure 58. burst read followed by asynchronous write using adv# ............................................................................. 165 table 58. burst read timing parameters ............................166 table 59. asynchronous write timing parameters using adv# ....................................................166 figure 59. asynchronous write followed by asynchronous read? adv# low...................................................................... 167 table 60. write timing parameters?adv# low .................167 table 61. read timing parameters?adv# low ..................168 figure 60. asynchronous write followed by asynchronous read ......................................................... 169 table 62. write timing parameters?asynchronous write followed by asynchronous read ........................................169 table 63. read timing parameters?asynchronous write followed by asynchronous read .....................................................170 how extended timings impact cellularram? operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 introduction ........................................................................................................ 170 asynchronous write operation ................................................................ 171 figure 61. extended timing for t cem.............................................. 171 figure 62. extended timing for t tm................................................ 171 table 64. extended cycle impact on read and write cycles 171 extended write timing? asynchronous write operation ...... 171 figure 63. extended write operation ................................ 172 page mode read operation ........................................................................ 172 burst-mode operation .................................................................................... 172 summary .............................................................................................................. 172 cellularram-2a features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 general description . . . . . . . . . . . . . . . . . . . . . . 173 figure 64. functional block diagram................................... 174 table 65. pin descriptions ................................................. 174 table 66. bus operations?asynchronous mode ................... 175 functional description . . . . . . . . . . . . . . . . . . . . .176 power-up initialization .................................................................................... 176 figure 65. power-up initialization timing ............................ 176 bus operating modes . . . . . . . . . . . . . . . . . . . . . 176 asynchronous mode ........................................................................................ 176 figure 66. read operation................................................ 177 figure 67. write operation .............................................. 177 page mode read operation ........................................................................ 177 figure 68. page mode read operation................................ 178 lb# / ub# operation ......................................................................................178 low power operation . . . . . . . . . . . . . . . . . . . . . 178 standby mode operation ...............................................................................178 temperature compensated refresh ...........................................................178 partial array refresh ........................................................................................ 179 deep power-down operation ..................................................................... 179 configuration register operation ...............................................................179 figure 69. load configuration register operation................. 180 table 67. configuration register bit mapping ....................... 181 table 68. 64mb address patterns for par (cr[4] = 1) .......... 181 absolute maximum ratings . . . . . . . . . . . . . . . . 182 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . 183 table 69. electrical characteristics and operating conditions . 183 table 70. temperature compensated refresh specifications and conditions ....................................................................... 183 table 71. partial array refresh specifications and conditions . 184 table 72. deep power-down specifications .......................... 184 table 73. capacitance specifications and conditions ............. 184 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . 184 figure 70. ac input/output reference waveform................. 184 figure 71. output load circuit ........................................... 184 table 74. output load circuit ............................................ 184 table 75. read cycle timing requirements ......................... 185 table 76. write cycle timing requirements ....................... 186 table 77. load configuration register timing requirements .. 186 table 78. deep power down timing requirements ............... 186 table 79. power-up initialization timing parameters ............. 187 figure 72. power-up initialization period ............................. 187 figure 73. load configuration register timing ..................... 187 table 80. load configuration register timing requirements .. 187 figure 74. deep power down entry/exit timing ................... 188 table 81. load configuration register timing requirements .. 188 figure 75. single read operation (we# = v ih ) ................... 188 table 82. read timing parameters .................................... 189 figure 76. page mode read operation (we# = v ih ) ............. 189 table 83. page mode read timing parameters .................... 189 figure 77. write cycle (we# control) ............................... 190 table 84. write timing parameters ..................................... 190 figure 78. write timing parameters (ce# control) ............... 191 table 85. write timing parameters (ce# control) ................ 191 figure 79. write cycle (lb# / ub# control)....................... 192 table 86. write timing parameters (lb# / ub# control) ....... 192 how extended timings impact cellularram? operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 introduction ........................................................................................................ 193 operation when page mode is disabled .................................................. 193 figure 80. extended timing for t cem.............................................. 193 figure 81. extended timing for t tm................................................ 193 operation when page mode is enabled .................................................... 193
6 S71GS256/128n_00_a0 december 17, 2004 advance information figure 82. extended timing for t cem (2) .............................. 194 impact on extended write operations .................................................. 194 figure 83. extended write operation ................................ 194 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 revision summary
december 17, 2004 S71GS256/128n_00_a0 7 advance information mcp block diagrams (256 mb flash + 64 mb psram) v io f-v cc ry/by# psram flash dq15 to dq0 flash-only address shared address f1-ce# r-ub# zz# r-ce1# r- v cc r-v cc r-v io f-v cc 22 wp#/acc oe# we# f-rst# ce# wp#/acc oe# we# f-rst# ry/by# v ss v ssq dq15 to dq0 16 i/o15 to i/o0 16 we# oe# ub# r-lb# lb# 22 r-ce1# 2 zz# f-v io
8 S71GS256/128n_00_a0 december 17, 2004 advance information (128 mb flash + 32 mb psram) v io f-v cc ry/by# psram flash dq15 to dq0 flash-only address shared address f1-ce# r-ub# r-ce1# r-v cc r-v cc r-v io f-v cc 21 wp#/acc oe# we# f-rst# ce# wp#/acc oe# we# f-rst# ry/by# v ss v ssq dq15 to dq0 16 i/o15 to i/o0 16 we# oe# ub# r-lb# lb# 21 r-ce1# 2 cre cre f-v io
december 17, 2004 S71GS256/128n_00_a0 9 advance information connection diagrams 256 mb flash + 64 mb psram pinout a7 a3 a2 dq8 dq14 r-ce1# r-lb# wp#/acc we# a8 a11 c3 c4 c5 c6 c7 c8 a6 r-ub# f-rst# rfu a19 a12 a15 d2 d3 d4 d5 d6 d7 d8 d9 a5 a18 ry/by# a20 a9 a13 a21 e2 e3 e4 e5 e6 e7 e8 e9 a1 a4 a17 a10 a14 a22 f2 f3 f4 f7 f8 f9 v ss dq1 a0 dq6 rfu a16 g3 g4 g2 g7 g8 g9 f1-ce# dq0 oe# dq9 dq3 dq4 dq13 dq15 zz# h2 h3 h4 h5 h6 h7 h8 h9 dq10 f-v cc r-v cc dq12 dq7 v ss j2 j3 j4 j5 j6 j7 j8 j9 dq2 dq11 rfu dq5 k3 k8 k4 k5 k6 k7 rfu a23 f5 rfu rfu g5 f6 g6 rfu rfu rfu rfu rfu rfu b3 b4 b5 b6 b7 b8 rfu rfu f-v cc rfu r-vio f-vio l3 l4 l5 l6 l7 l8 b2 b9 c9 c2 k2 k9 l9 l2 rfu rfu rfu rfu rfu rfu rfu rfu a1 a10 m1 m10 dnu dnu dnu dnu ram only shared flash only legend reserved fo r future use 84-ball fine-pitch ball grid array 256 mb flash + 64 mb psram pinout (top view, balls facing down)
10 S71GS256/128n_00_a0 december 17, 2004 advance information 128 mb flash + 32 mb psram pinout a7 a3 a2 dq8 dq14 r-ce1# r-lb# wp#/acc we# a8 a11 c3 c4 c5 c6 c7 c8 a6 r-ub# f-rst# rfu a19 a12 a15 d2 d3 d4 d5 d6 d7 d8 d9 a5 a18 ry/by# a20 a9 a13 a21 e2 e3 e4 e5 e6 e7 e8 e9 a1 a4 a17 a10 a14 a22 f2 f3 f4 f7 f8 f9 v ss dq1 a0 dq6 rfu a16 g3 g4 g2 g7 g8 g9 f1-ce# dq0 oe# dq9 dq3 dq4 dq13 dq15 cre h2 h3 h4 h5 h6 h7 h8 h9 dq10 f-v cc r-v cc dq12 dq7 v ss j2 j3 j4 j5 j6 j7 j8 j9 dq2 dq11 rfu dq5 k3 k8 k4 k5 k6 k7 rfu rfu f5 rfu rfu g5 f6 g6 rfu rfu rfu rfu rfu rfu b3 b4 b5 b6 b7 b8 rfu rfu f-v cc rfu r-vio f-vio l3 l4 l5 l6 l7 l8 b2 b9 c9 c2 k2 k9 l9 l2 rfu rfu rfu rfu rfu rfu rfu rfu a1 a10 m1 m10 dnu dnu dnu dnu ram only shared flash only legend reserved fo r future use 84-ball fine-pitch ball grid array 128 mb flash + 32 mb psram pinout (top view, balls facing down)
december 17, 2004 S71GS256/128n_00_a0 11 advance information input/output descriptions a23-a0 = 24 address inputs (256 mb) a22-a0 = 23 address inputs (128 mb) dq15-dq0 = data input/output oe# = output enable input. asynchronous relative to clk for the burst mode. we# = write enable input. v ss = ground nc = no connect; not connected internally f-rst# = hardware reset input. low = device resets and returns to reading array data wp#/acc = hardware write protect input / programming acceleration input. r-ce1# = chip-enable input for psram. zz# = psram sleep mode cre = configuration register enable. cre is used only for power savings, but does not enable burst operations. f1-ce# = chip-enable input for flash 1. f-v cc = flash 3.0 volt-only single power supply. r-v cc = psram power supply. r-ub# = upper byte control (psram). r-lb# = lower byte control (psram). rfu = reserved for future use. ry/by# = ready/busy output. f-v io = flash input/output buffer power supply r-v io = psram input/output buffer power supply
12 S71GS256/128n_00_a0 december 17, 2004 advance information logic symbol notes: 1. max = 24 [256 mb flash], 23 [128 mb flash]. 2. amax = a23 [256 mb flash], a22 [128 mb flash]. 3. cre is available only in synchronous psram. 4. zz# is available only in asynchronous psram. max (note 1) 16 dq15?dq0 amax (note 2) ?a0 we# wp#/acc we# f-rst# r-ce1# ry/by# ub# oe# f1-ce# cre (note 3) zz# (note 4)
december 17, 2004 S71GS256/128n_00_a0 13 advance information ordering information the order number (valid combination) is formed by the following: s71gs 256 n c0 ba w ak 0 packing type 0=tray 2 = 7? tape and reel 3=13? tape and reel package modifier / model number see valid combinations table temperature range w = wireless (-25 c to +85 c) package type ba = very thin fine-pitch bga lead (pb)-free compliant package bf = very thin fine-pitch bga lead (pb)-free package psram density c0 = 64 mb psram b0 = 32 mb psram process technology n = 110 nm, mirrorbit tm technology flash density 256 = 256 mb 128 = 128 mb product family s71gs multi-chip product (mcp) 3.0 volt-only v cc and 1.8 v v io uniform sector page mode flash memory with 1.8 volt psram S71GS256nc0 valid combinations flash initial/page speed (ns) address sector protection (p)sram supplier (p)sram type/ access time (ns) package type package marking base ordering part number package & temperature package modifier/ model number packing type S71GS256nc0 baw ak 0, 2, 3 (note 1) 110/30 lowest add cellram 2a (note 3) 70 / 25 8mmx11.6mm 84-ball lead (pb)-free compliant (note 2) ap highest add S71GS256nc0 bfw ak lowest add 8mmx11.6mm 84-ball lead (pb)-free ap highest add notes: 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. 3. for specifications, refer to the cellularram 2a module. valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations.
14 S71GS256/128n_00_a0 december 17, 2004 advance information s71gs128nb0 valid combinations flash initial/page speed (ns) address sector protection (p)sram supplier (p)sram type/ access time (ns) package type package marking base ordering part number package & temperature package modifier/ model number packing type s71gs128nb0 baw ak 0, 2, 3 (note 1) 110/30 lowest add cellram 2 (note 3) 70 / 25 8mmx11.6mm 84-ball lead (pb)-free compliant (note 2) ap highest add s71gs128nb0 bfw ak lowest add 8mmx11.6mm 84-ball lead (pb)-free ap highest add notes: 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. 3. for specifications, refer to the cellularram 2 module. valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations.
december 17, 2004 S71GS256/128n_00_a0 15 advance information physical dimensions tla084?84-ball fine-pitch ball grid array (fbga) 8.0 x 11.6 x1.2 mm mcp compatible package 3372-2 \ 16-038.22a package tla 084 jedec n/a d x e 11.60 mm x 8.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.97 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 84 ball count ? b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b10,c1,c10,d1,d10, e1,e10,f1,f10,g1,g10, h1,h10,j1,j10,k1,k10,l1,l10, m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 84x a1 a2 a 0.15 c a b m c m 0.08 pin a1 ml e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd bottom view
this document contains information on a product under development at spansion llc. the information is intended to help you eval uate this product. spansion llc reserves the right to change or discontinue work on this proposed product without notice. publication number s29glxxxn_mcp revision a amendment 1 issue date december 15, 2004 advance information s29glxxxn mirrorbit tm flash family s29gl512n, s29gl256n, s29gl128n 512 megabit, 256 megabit, and 128 megabit, 3.0 volt-only page mode flash memory featuring 110 nm mirrorbit process technology data sheet distinctive characteristics architectural advantages ? single power supply operation ? 3 volt read, erase, and program operations ? enhanced versatilei/o ? control ? all input levels (address, control, and dq input levels) and outputs are determined by voltage on v io input. v io range is 1.65 to v cc ? manufactured on 110 nm mirrorbit process technology ? secured silicon sector region ? 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random electronic serial number, accessible through a command sequence ? may be programmed and locked at the factory or by the customer ? flexible sector architecture ? s29gl512n: five hundred twelve 64 kword (128 kbyte) sectors ? s29gl256n: two hundred fifty-six 64 kword (128 kbyte) sectors ? s29gl128n: one hundred twenty-eight 64 kword (128 kbyte) sectors ? compatibility with jedec standards ? provides pinout and software compatibility for single- power supply flash, and superior inadvertent write protection ? 100,000 erase cycles per sector typical ? 20-year data retention typical performance characteristics ? high performance ? 90 ns access time (s29gl128n, s29gl256n, s29gl512n) ? 8-word/16-byte page read buffer ? 25 ns page read times ? 16-word/32-byte write buffer reduces overall programming time for multiple-word updates ? low power consumption (typical values at 3.0 v, 5 mhz) ? 25 ma typical active read current; ? 50 ma typical erase/program current ? 1 a typical standby mode current software & hardware features ? software features ? program suspend & resume: read other sectors before programming operation is completed ? erase suspend & resume: read/program other sectors before an erase operation is completed ? data# polling & toggle bits provide status ? unlock bypass program command reduces overall multiple-word programming time ? cfi (common flash interfac e) compliant: allows host system to identify and accommodate multiple flash devices ? hardware features ? advanced sector protection ? wp#/acc input accelerates programming time (when high voltage is applied) for greater throughput during system production. protects first or last sector regardless of sector protection settings ? hardware reset input (reset#) resets device ? ready/busy# output (ry/by#) detects program or erase cycle completion
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 17 advance information general description the s29gl512/256/128n family of devices are 3.0v single power flash memory manufactured using 110 nm mirrorbit technology. the s29gl512n is a 512 mbit, organized as 33,554,432 words or 67,108,864 bytes. the s29gl256n is a 256 mbit, organized as 16,777,216 words or 33,554,432 bytes. the s29gl128n is a 128 mbit, organized as 8,388,608 words or 16,777,216 bytes. the device can be programmed either in the host system or in standard eprom programmers. access times as fast as 90 ns (s29gl128n, s29gl256n, s29gl512n) are avail- able. note that each access time has a specific operating voltage range (v cc ) and an i/o voltage range (v io ), as specified in the ?product selector guide? section. the devices are offered in a 56-pin tsop or 64-ball fortified bga package. each device has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. each device requires only a single 3.0 volt power supply for both read and write functions. in addition to a v cc input, a high-voltage accelerated program ( wp#/ acc) input provides shorter programming times through increased cur- rent. this feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. the devices are entirely command set compatible with the jedec single- power-supply flash standard . commands are written to the device using standard microprocessor write timing. write cycles also internally latch addresses and data needed for the programming and erase operations. the sector erase architecture allows memory sectors to be erased and repro- grammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. device programming and erasure are initiated through command sequences. once a program or erase operation has begun, the host system need only poll the dq7 (data# polling) or dq6 (toggle) status bits or monitor the ready/busy# (ry/by#) output to determine whether the operation is complete. to facilitate programming, an unlock bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four. the enhanced versatilei/o? (v io ) control allows the host system to set the voltage levels that the device generates and tolerates on all input levels (address, chip control, and dq input levels) to the same voltage level that is asserted on the v io pin. this allows the device to operate in a 1.8 v or 3 v system environ- ment as required. hardware data protection measures include a low v cc detector that automat- ically inhibits write operations during power transitions. persistent sector protection provides in-system, command-enabled protection of any combina- tion of sectors using a single power supply at v cc . password sector protection prevents unauthorized write and erase operations in any combination of sectors through a user-defined 64-bit password. the erase suspend/erase resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. the program suspend/program resume fea- ture enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation. the hardware reset# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. the reset# pin may be
18 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information tied to the system reset circuitry. a system reset would thus also reset the device, enabling the host system to read boot-up firmware from the flash memory device. the device reduces power consumption in the standby mode when it detects specific voltage levels on ce# and reset#, or when addresses have been stable for a specified period of time. the secured silicon sector provides a 128-word/256-byte area for code or data that can be permanently protected. once this sector is protected, no further changes within the sector can occur. the write protect (wp#/acc) feature protects the first or last sector by as- serting a logic low on the wp# pin. mirrorbit flash technology combines years of flash memory manufacturing expe- rience to produce the highest levels of quality, reliability and cost effectiveness. the device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. the data is programmed using hot electron injection.
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 19 advance information product selector guide s29gl512n s29gl256n s29gl128n part number s29gl512n speed option v cc = 2.7?3.6 v v io = 2.7?3.6 v 10 11 v io = 1.65?1.95 v 11 v cc = 3.0-3.6v v io = 3.0-3.6v 90 max. access time (ns) 90 100 110 110 max. ce# access time (ns) 90 100 110 110 max. page access time (ns) 25 25 25 30 max. oe# access time (ns) 25 25 25 30 part number s29gl256n speed option v cc = 2.7?3.6 v v io = 2.7?3.6 v 10 11 v io = 1.65?1.95 v 11 v cc = regulated (3.0-3.6v) v io = regulated (3.0-3.6v) 90 max. access time (ns) 90 100 110 110 max. ce# access time (ns) 90 100 110 110 max. page access time (ns) 25 25 25 30 max. oe# access time (ns) 25 25 25 30 part number s29gl128n speed option v cc = 2.7?3.6 v v io = 2.7?3.6 v 10 11 v io = 1.65?1.95 v 11 v cc = regulated (3.0-3.6v) v io = regulated (3.0-3.6v) 90 max. access time (ns) 90 100 110 110 max. ce# access time (ns) 90 100 110 110 max. page access time (ns) 25 25 25 30 max. oe# access time (ns) 25 25 25 30
20 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information block diagram notes: 1. a max gl512n = a24, a max gl256n = a23, a max gl128n = a22 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss v io we# wp#/acc ce# oe# stb stb dq15 ? dq0 (a-1) sector switches ry/by# reset# data latch y-gating cell matrix address latch a max **?a0
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 21 advance information pin description a24?a0 = 25 address inputs (512 mb) a23?a0 = 24 address inputs (256 mb) a22?a0 = 23 address inputs (128 mb) dq14?dq0 = 15 data inputs/outputs dq15/a-1 = dq15 (data input/output, word mode), a-1 (lsb address input ce# = chip enable input oe# = output enable input we# = write enable input wp#/acc = hardware write protect input; acceleration input reset# = hardware reset pin input ry/by# = ready/busy output v cc = 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v io = output buffer power v ss =device ground nc = pin not connected internally
22 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information logic symbol s29gl512n s29gl256n s29gl128n 25 16 or 8 dq15?dq0 (a-1) a24?a0 ce# oe# we# reset# ry/by# wp#/acc v io 24 16 or 8 dq15?dq0 (a-1) a23?a0 ce# oe# we# reset# ry/by# wp#/acc v io 23 16 or 8 dq15?dq0 (a-1) a22?a0 ce# oe# we# reset# ry/by# wp#/acc v io
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 23 advance information device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. ta b l e 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. ta b l e 1 . device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 11.5?12.5v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. addresses are amax:a0 in word mode. sector addresses are a max :a16 in both modes. 2. if wp# = v il , the first or last sector group remains protected. if wp# = v ih , the first or last sector will be protected or unprotected as determined by the method described in ?write protect (wp#)?. all sectors are unprotected when shipped from the factory (the secured silicon sector may be factory protected depending on version ordered.) 3. d in or d out as required by command sequence, data polling, or sector protect algorithm (see figure 2 , figure 4 , and figure 5 ). ve rs at il e i o tm (v io ) control the versatileio tm (v io ) control allows the host system to set the voltage levels that the device generates and tolerates on ce# and dq i/os to the same voltage level that is asserted on v io . see ordering information for v io options on this device. for example, a v i/o of 1.65 v to 3.6 v allows for i/o at the 1.8 or 3 volt levels, driving and receiving signals to and from other 1.8-v or 3-v devices on the same data bus. requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output control and gates array data to the output pins. we# should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory operation ce# oe# we# reset# wp#/ acc addresses (note 1) dq0?dq15 read l l h h x a in d out write (program/erase) l h l h note 2 a in (note 3) accelerated program l h l h v hh a in (note 3) standby v cc 0.3 v x x v cc 0.3 v hxhigh-z output disable l h h h x x high-z reset x x x l x x high-z
24 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see ?reading array data? on page 66 for more information. refer to the ac read- only operations table for timing specifications and to figure 11 for the timing di- agram. refer to the dc characteristics table for the active current specification on reading array data. page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read operation. this mode provides faster read access speed for random locations within a page. the page size of the device is 8 words/16 bytes. the appropriate page is selected by the higher address bits a(max)?a3. address bits a2?a0 determine the specific word within a page. this is an asynchronous operation; the microprocessor supplies the specific word location. the random or initial page access is equal to t acc or t ce and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t pacc . when ce# is de-asserted and reasserted for a subsequent access, the access time is t acc or t ce . fast page mode accesses are obtained by keeping the ?read-page addresses? constant and changing the ?intra-read page? addresses. writing commands/command sequences to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . the device features an unlock bypass mode to facilitate faster programming. once the device enters the unlock bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. the ?word program command sequence? section has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sectors, or the entire device. ta b l e 2 , ta b l e 4 , and ta b l e 5 indicate the address space that each sector occupies. refer to the dc characteristics table for the active current specification for the write mode. the ac characteristics section contains timing specification tables and timing diagrams for write operations. write buffer write buffer programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. this results in faster effective programming time than the standard programming algorithms. see ?write buffer? for more information. accelerated program operation the device offers accelerated program operations through the acc function. this is one of two functions provided by the wp#/acc pin. this function is primarily intended to allow faster manufacturing throughput at the factory.
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 25 advance information if the system asserts v hh on this pin, the device automatically enters the afore- mentioned unlock bypass mode, temporarily unprotects any protected sector groups, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle program command se- quence as required by the unlock bypass mode. removing v hh from the wp#/ acc pin returns the device to normal operation. note that the wp#/acc pin must not be at v hh for operations other than accelerated programming, or device dam- age may result. wp# has an internal pullup; when unconnected, wp# is at v ih . autoselect functions if the system writes the autoselect command sequence, the device enters the au- toselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the ?autoselect mode? section on page 52 and ?autoselect command sequence? section on page 66 sections for more information. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# pins are both held at v io 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v io 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or programming, the device draws ac- tive current until the operation is completed. refer to the ?dc characteristics? section on page 90 for the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the de- vice automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# con- trol signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. refer to the ?dc characteristics? section on page 90 for the automatic sleep mode current specification. reset#: hardware reset pin the reset# pin provides a hardware method of resetting the device to reading array data. when the reset# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the op- eration that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.
26 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information current is reduced for the duration of th e reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc5 ). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm- ware from the flash memory. refer to the ac characteristics tables for reset# parameters and to figure 13 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state. ta b l e 2 . sector address table?s29gl512n sector a24?a16 sector size (kbytes/ kwords) address range (in hexadecimal) sa0 0 0 0 0 0 0 0 0 0 128/64 0000000?000ffff sa1 0 0 0 0 0 0 0 0 1 128/64 0010000?001ffff sa2 0 0 0 0 0 0 0 1 0 128/64 0020000?002ffff sa3 0 0 0 0 0 0 0 1 1 128/64 0030000?003ffff sa4 0 0 0 0 0 0 1 0 0 128/64 0040000?004ffff sa5 0 0 0 0 0 0 1 0 1 128/64 0050000?005ffff sa6 0 0 0 0 0 0 1 1 0 128/64 0060000?006ffff sa7 0 0 0 0 0 0 1 1 1 128/64 0070000?007ffff sa8 0 0 0 0 0 1 0 0 0 128/64 0080000?008ffff sa9 0 0 0 0 0 1 0 0 1 128/64 0090000?009ffff sa10 0 0 0 0 0 1 0 1 0 128/64 00a0000?00affff sa11 0 0 0 0 0 1 0 1 1 128/64 00b0000?00bffff sa12 0 0 0 0 0 1 1 0 0 128/64 00c0000?00cffff sa13 0 0 0 0 0 1 1 0 1 128/64 00d0000?00dffff sa14 0 0 0 0 0 1 1 1 0 128/64 00e0000?00effff sa15 0 0 0 0 0 1 1 1 1 128/64 00f0000?00fffff sa16 0 0 0 0 1 0 0 0 0 128/64 0100000?010ffff sa17 0 0 0 0 1 0 0 0 1 128/64 0110000?011ffff sa18 0 0 0 0 1 0 0 1 0 128/64 0120000?012ffff sa19 0 0 0 0 1 0 0 1 1 128/64 0130000?013ffff sa20 0 0 0 0 1 0 1 0 0 128/64 0140000?014ffff sa21 0 0 0 0 1 0 1 0 1 128/64 0150000?015ffff sa22 0 0 0 0 1 0 1 1 0 128/64 0160000?016ffff sa23 0 0 0 0 1 0 1 1 1 128/64 0170000?017ffff
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 27 advance information sa24 0 0 0 0 1 1 0 0 0 128/64 0180000?018ffff sa25 0 0 0 0 1 1 0 0 1 128/64 0190000?019ffff sa26 0 0 0 0 1 1 0 1 0 128/64 01a0000?01affff sa27 0 0 0 0 1 1 0 1 1 128/64 01b0000?01bffff sa28 0 0 0 0 1 1 1 0 0 128/64 01c0000?01cffff sa29 0 0 0 0 1 1 1 0 1 128/64 01d0000?01dffff sa30 0 0 0 0 1 1 1 1 0 128/64 01e0000?01effff sa31 0 0 0 0 1 1 1 1 1 128/64 01f0000?01fffff sa32 0 0 0 1 0 0 0 0 0 128/64 0200000?020ffff sa33 0 0 0 1 0 0 0 0 1 128/64 0210000?021ffff sa34 0 0 0 1 0 0 0 1 0 128/64 0220000?022ffff sa35 0 0 0 1 0 0 0 1 1 128/64 0230000?023ffff sa36 0 0 0 1 0 0 1 0 0 128/64 0240000?024ffff sa37 0 0 0 1 0 0 1 0 1 128/64 0250000?025ffff sa38 0 0 0 1 0 0 1 1 0 128/64 0260000?026ffff sa39 0 0 0 1 0 0 1 1 1 128/64 0270000?027ffff sa40 0 0 0 1 0 1 0 0 0 128/64 0280000?028ffff sa41 0 0 0 1 0 1 0 0 1 128/64 0290000?029ffff sa42 0 0 0 1 0 1 0 1 0 128/64 02a0000?02affff sa43 0 0 0 1 0 1 0 1 1 128/64 02b0000?02bffff sa44 0 0 0 1 0 1 1 0 0 128/64 02c0000?02cffff sa45 0 0 0 1 0 1 1 0 1 128/64 02d0000?02dffff sa46 0 0 0 1 0 1 1 1 0 128/64 02e0000?02effff sa47 0 0 0 1 0 1 1 1 1 128/64 02f0000?02fffff sa48 0 0 0 1 1 0 0 0 0 128/64 0300000?030ffff sa49 0 0 0 1 1 0 0 0 1 128/64 0310000?031ffff sa50 0 0 0 1 1 0 0 1 0 128/64 0320000?032ffff sa51 0 0 0 1 1 0 0 1 1 128/64 0330000?033ffff sa52 0 0 0 1 1 0 1 0 0 128/64 0340000?034ffff sa53 0 0 0 1 1 0 1 0 1 128/64 0350000?035ffff sa54 0 0 0 1 1 0 1 1 0 128/64 0360000?036ffff sa55 0 0 0 1 1 0 1 1 1 128/64 0370000?037ffff sa56 0 0 0 1 1 1 0 0 0 128/64 0380000?038ffff sa57 0 0 0 1 1 1 0 0 1 128/64 0390000?039ffff sa58 0 0 0 1 1 1 0 1 0 128/64 03a0000?03affff table 2. sector address table?s29gl512n (continued) sector a24?a16 sector size (kbytes/ kwords) address range (in hexadecimal)
28 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information sa59 0 0 0 1 1 1 0 1 1 128/64 03b0000?03bffff sa60 0 0 0 1 1 1 1 0 0 128/64 03c0000?03cffff sa61 0 0 0 1 1 1 1 0 1 128/64 03d0000?03dffff sa62 0 0 0 1 1 1 1 1 0 128/64 03e0000?03effff sa63 0 0 0 1 1 1 1 1 1 128/64 03f0000?03fffff sa64 0 0 1 0 0 0 0 0 0 128/64 0400000?040ffff sa65 0 0 1 0 0 0 0 0 1 128/64 0410000?041ffff sa66 0 0 1 0 0 0 0 1 0 128/64 0420000?042ffff sa67 0 0 1 0 0 0 0 1 1 128/64 0430000?043ffff sa68 0 0 1 0 0 0 1 0 0 128/64 0440000?044ffff sa69 0 0 1 0 0 0 1 0 1 128/64 0450000?045ffff sa70 0 0 1 0 0 0 1 1 0 128/64 0460000?046ffff sa71 0 0 1 0 0 0 1 1 1 128/64 0470000?047ffff sa72 0 0 1 0 0 1 0 0 0 128/64 0480000?048ffff sa73 0 0 1 0 0 1 0 0 1 128/64 0490000?049ffff sa74 0 0 1 0 0 1 0 1 0 128/64 04a0000?04affff sa75 0 0 1 0 0 1 0 1 1 128/64 04b0000?04bffff sa76 0 0 1 0 0 1 1 0 0 128/64 04c0000?04cffff sa77 0 0 1 0 0 1 1 0 1 128/64 04d0000?04dffff sa78 0 0 1 0 0 1 1 1 0 128/64 04e0000?04effff sa79 0 0 1 0 0 1 1 1 1 128/64 04f0000?04fffff sa80 0 0 1 0 1 0 0 0 0 128/64 0500000?050ffff sa81 0 0 1 0 1 0 0 0 1 128/64 0510000?051ffff sa82 0 0 1 0 1 0 0 1 0 128/64 0520000?052ffff sa83 0 0 1 0 1 0 0 1 1 128/64 0530000?053ffff sa84 0 0 1 0 1 0 1 0 0 128/64 0540000?054ffff sa85 0 0 1 0 1 0 1 0 1 128/64 0550000?055ffff sa86 0 0 1 0 1 0 1 1 0 128/64 0560000?056ffff sa87 0 0 1 0 1 0 1 1 1 128/64 0570000?057ffff sa88 0 0 1 0 1 1 0 0 0 128/64 0580000?058ffff sa89 0 0 1 0 1 1 0 0 1 128/64 0590000?059ffff sa90 0 0 1 0 1 1 0 1 0 128/64 05a0000?05affff sa91 0 0 1 0 1 1 0 1 1 128/64 05b0000?05bffff sa92 0 0 1 0 1 1 1 0 0 128/64 05c0000?05cffff sa93 0 0 1 0 1 1 1 0 1 128/64 05d0000?05dffff table 2. sector address table?s29gl512n (continued) sector a24?a16 sector size (kbytes/ kwords) address range (in hexadecimal)
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 29 advance information sa94 0 0 1 0 1 1 1 1 0 128/64 05e0000?05effff sa95 0 0 1 0 1 1 1 1 1 128/64 05f0000?05fffff sa96 0 0 1 1 0 0 0 0 0 128/64 0600000?060ffff sa97 0 0 1 1 0 0 0 0 1 128/64 0610000?061ffff sa98 0 0 1 1 0 0 0 1 0 128/64 0620000?062ffff sa99 0 0 1 1 0 0 0 1 1 128/64 0630000?063ffff sa100 0 0 1 1 0 0 1 0 0 128/64 0640000?064ffff sa101 0 0 1 1 0 0 1 0 1 128/64 0650000?065ffff sa102 0 0 1 1 0 0 1 1 0 128/64 0660000?066ffff sa103 0 0 1 1 0 0 1 1 1 128/64 0670000?067ffff sa104 0 0 1 1 0 1 0 0 0 128/64 0680000?068ffff sa105 0 0 1 1 0 1 0 0 1 128/64 0690000?069ffff sa106 0 0 1 1 0 1 0 1 0 128/64 06a0000?06affff sa107 0 0 1 1 0 1 0 1 1 128/64 06b0000?06bffff sa108 0 0 1 1 0 1 1 0 0 128/64 06c0000?06cffff sa109 0 0 1 1 0 1 1 0 1 128/64 06d0000?06dffff sa110 0 0 1 1 0 1 1 1 0 128/64 06e0000?06effff sa111 0 0 1 1 0 1 1 1 1 128/64 06f0000?06fffff sa112 0 0 1 1 1 0 0 0 0 128/64 0700000?070ffff sa113 0 0 1 1 1 0 0 0 1 128/64 0710000?071ffff sa114 0 0 1 1 1 0 0 1 0 128/64 0720000?072ffff sa115 0 0 1 1 1 0 0 1 1 128/64 0730000?073ffff sa116 0 0 1 1 1 0 1 0 0 128/64 0740000?074ffff sa117 0 0 1 1 1 0 1 0 1 128/64 0750000?075ffff sa118 0 0 1 1 1 0 1 1 0 128/64 0760000?076ffff sa119 0 0 1 1 1 0 1 1 1 128/64 0770000?077ffff sa120 0 0 1 1 1 1 0 0 0 128/64 0780000?078ffff sa121 0 0 1 1 1 1 0 0 1 128/64 0790000?079ffff sa122 0 0 1 1 1 1 0 1 0 128/64 07a0000?07affff sa123 0 0 1 1 1 1 0 1 1 128/64 07b0000?07bffff sa124 0 0 1 1 1 1 1 0 0 128/64 07c0000?07cffff sa125 0 0 1 1 1 1 1 0 1 128/64 07d0000?07dffff sa126 0 0 1 1 1 1 1 1 0 128/64 07e0000?07effff sa127 0 0 1 1 1 1 1 1 1 128/64 07f0000?07fffff sa128 0 1 0 0 0 0 0 0 0 128/64 0800000?080ffff table 2. sector address table?s29gl512n (continued) sector a24?a16 sector size (kbytes/ kwords) address range (in hexadecimal)
30 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information sa129 0 1 0 0 0 0 0 0 1 128/64 0810000?081ffff sa130 0 1 0 0 0 0 0 1 0 128/64 0820000?082ffff sa131 0 1 0 0 0 0 0 1 1 128/64 0830000?083ffff sa132 0 1 0 0 0 0 1 0 0 128/64 0840000?084ffff sa133 0 1 0 0 0 0 1 0 1 128/64 0850000?085ffff sa134 0 1 0 0 0 0 1 1 0 128/64 0860000?086ffff sa135 0 1 0 0 0 0 1 1 1 128/64 0870000?087ffff sa136 0 1 0 0 0 1 0 0 0 128/64 0880000?088ffff sa137 0 1 0 0 0 1 0 0 1 128/64 0890000?089ffff sa138 0 1 0 0 0 1 0 1 0 128/64 08a0000?08affff sa139 0 1 0 0 0 1 0 1 1 128/64 08b0000?08bffff sa140 0 1 0 0 0 1 1 0 0 128/64 08c0000?08cffff sa141 0 1 0 0 0 1 1 0 1 128/64 08d0000?08dffff sa142 0 1 0 0 0 1 1 1 0 128/64 08e0000?08effff sa143 0 1 0 0 0 1 1 1 1 128/64 08f0000?08fffff sa144 0 1 0 0 1 0 0 0 0 128/64 0900000?090ffff sa145 0 1 0 0 1 0 0 0 1 128/64 0910000?091ffff sa146 0 1 0 0 1 0 0 1 0 128/64 0920000?092ffff sa147 0 1 0 0 1 0 0 1 1 128/64 0930000?093ffff sa148 0 1 0 0 1 0 1 0 0 128/64 0940000?094ffff sa149 0 1 0 0 1 0 1 0 1 128/64 0950000?095ffff sa150 0 1 0 0 1 0 1 1 0 128/64 0960000?096ffff sa151 0 1 0 0 1 0 1 1 1 128/64 0970000?097ffff sa152 0 1 0 0 1 1 0 0 0 128/64 0980000?098ffff sa153 0 1 0 0 1 1 0 0 1 128/64 0990000?099ffff sa154 0 1 0 0 1 1 0 1 0 128/64 09a0000?09affff sa155 0 1 0 0 1 1 0 1 1 128/64 09b0000?09bffff sa156 0 1 0 0 1 1 1 0 0 128/64 09c0000?09cffff sa157 0 1 0 0 1 1 1 0 1 128/64 09d0000?09dffff sa158 0 1 0 0 1 1 1 1 0 128/64 09e0000?09effff sa159 0 1 0 0 1 1 1 1 1 128/64 09f0000?09fffff sa160 0 1 0 1 0 0 0 0 0 128/64 0a00000?0a0ffff sa161 0 1 0 1 0 0 0 0 1 128/64 0a10000?0a1ffff sa162 0 1 0 1 0 0 0 1 0 128/64 0a20000?0a2ffff sa163 0 1 0 1 0 0 0 1 1 128/64 0a30000?0a3ffff table 2. sector address table?s29gl512n (continued) sector a24?a16 sector size (kbytes/ kwords) address range (in hexadecimal)
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 31 advance information sa164 0 1 0 1 0 0 1 0 0 128/64 0a40000?0a4ffff sa165 0 1 0 1 0 0 1 0 1 128/64 0a50000?0a5ffff sa166 0 1 0 1 0 0 1 1 0 128/64 0a60000?0a6ffff sa167 0 1 0 1 0 0 1 1 1 128/64 0a70000?0a7ffff sa168 0 1 0 1 0 1 0 0 0 128/64 0a80000?0a8ffff sa169 0 1 0 1 0 1 0 0 1 128/64 0a90000?0a9ffff sa170 0 1 0 1 0 1 0 1 0 128/64 0aa0000?0aaffff sa171 0 1 0 1 0 1 0 1 1 128/64 0ab0000?0abffff sa172 0 1 0 1 0 1 1 0 0 128/64 0ac0000?0acffff sa173 0 1 0 1 0 1 1 0 1 128/64 0ad0000?0adffff sa174 0 1 0 1 0 1 1 1 0 128/64 0ae0000?0aeffff sa175 0 1 0 1 0 1 1 1 1 128/64 0af0000?0afffff sa176 0 1 0 1 1 0 0 0 0 128/64 0b00000?0b0ffff sa177 0 1 0 1 1 0 0 0 1 128/64 0b10000?0b1ffff sa178 0 1 0 1 1 0 0 1 0 128/64 0b20000?0b2ffff sa179 0 1 0 1 1 0 0 1 1 128/64 0b30000?0b3ffff sa180 0 1 0 1 1 0 1 0 0 128/64 0b40000?0b4ffff sa181 0 1 0 1 1 0 1 0 1 128/64 0b50000?0b5ffff sa182 0 1 0 1 1 0 1 1 0 128/64 0b60000?0b6ffff sa183 0 1 0 1 1 0 1 1 1 128/64 0b70000?0b7ffff sa184 0 1 0 1 1 1 0 0 0 128/64 0b80000?0b8ffff sa185 0 1 0 1 1 1 0 0 1 128/64 0b90000?0b9ffff sa186 0 1 0 1 1 1 0 1 0 128/64 0ba0000?0baffff sa187 0 1 0 1 1 1 0 1 1 128/64 0bb0000?0bbffff sa188 0 1 0 1 1 1 1 0 0 128/64 0bc0000?0bcffff sa189 0 1 0 1 1 1 1 0 1 128/64 0bd0000?0bdffff sa190 0 1 0 1 1 1 1 1 0 128/64 0be0000?0beffff sa191 0 1 0 1 1 1 1 1 1 128/64 0bf0000?0bfffff sa192 0 1 1 0 0 0 0 0 0 128/64 0c00000?0c0ffff sa193 0 1 1 0 0 0 0 0 1 128/64 0c10000?0c1ffff sa194 0 1 1 0 0 0 0 1 0 128/64 0c20000?0c2ffff sa195 0 1 1 0 0 0 0 1 1 128/64 0c30000?0c3ffff sa196 0 1 1 0 0 0 1 0 0 128/64 0c40000?0c4ffff sa197 0 1 1 0 0 0 1 0 1 128/64 0c50000?0c5ffff sa198 0 1 1 0 0 0 1 1 0 128/64 0c60000?0c6ffff table 2. sector address table?s29gl512n (continued) sector a24?a16 sector size (kbytes/ kwords) address range (in hexadecimal)
32 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information sa199 0 1 1 0 0 0 1 1 1 128/64 0c70000?0c7ffff sa200 0 1 1 0 0 1 0 0 0 128/64 0c80000?0c8ffff sa201 0 1 1 0 0 1 0 0 1 128/64 0c90000?0c9ffff sa202 0 1 1 0 0 1 0 1 0 128/64 0ca0000?0caffff sa203 0 1 1 0 0 1 0 1 1 128/64 0cb0000?0cbffff sa204 0 1 1 0 0 1 1 0 0 128/64 0cc0000?0ccffff sa205 0 1 1 0 0 1 1 0 1 128/64 0cd0000?0cdffff sa206 0 1 1 0 0 1 1 1 0 128/64 0ce0000?0ceffff sa207 0 1 1 0 0 1 1 1 1 128/64 0cf0000?0cfffff sa208 0 1 1 0 1 0 0 0 0 128/64 0d00000?0d0ffff sa209 0 1 1 0 1 0 0 0 1 128/64 0d10000?0d1ffff sa210 0 1 1 0 1 0 0 1 0 128/64 0d20000?0d2ffff sa211 0 1 1 0 1 0 0 1 1 128/64 0d30000?0d3ffff sa212 0 1 1 0 1 0 1 0 0 128/64 0d40000?0d4ffff sa213 0 1 1 0 1 0 1 0 1 128/64 0d50000?0d5ffff sa214 0 1 1 0 1 0 1 1 0 128/64 0d60000?0d6ffff sa215 0 1 1 0 1 0 1 1 1 128/64 0d70000?0d7ffff sa216 0 1 1 0 1 1 0 0 0 128/64 0d80000?0d8ffff sa217 0 1 1 0 1 1 0 0 1 128/64 0d90000?0d9ffff sa218 0 1 1 0 1 1 0 1 0 128/64 0da0000?0daffff sa219 0 1 1 0 1 1 0 1 1 128/64 0db0000?0dbffff sa220 0 1 1 0 1 1 1 0 0 128/64 0dc0000?0dcffff sa221 0 1 1 0 1 1 1 0 1 128/64 0dd0000?0ddffff sa222 0 1 1 0 1 1 1 1 0 128/64 0de0000?0deffff sa223 0 1 1 0 1 1 1 1 1 128/64 0df0000?0dfffff sa224 0 1 1 1 0 0 0 0 0 128/64 0e00000?0e0ffff sa225 0 1 1 1 0 0 0 0 1 128/64 0e10000?0e1ffff sa226 0 1 1 1 0 0 0 1 0 128/64 0e20000?0e2ffff sa227 0 1 1 1 0 0 0 1 1 128/64 0e30000?0e3ffff sa228 0 1 1 1 0 0 1 0 0 128/64 0e40000?0e4ffff sa229 0 1 1 1 0 0 1 0 1 128/64 0e50000?0e5ffff sa230 0 1 1 1 0 0 1 1 0 128/64 0e60000?0e6ffff sa231 0 1 1 1 0 0 1 1 1 128/64 0e70000?0e7ffff sa232 0 1 1 1 0 1 0 0 0 128/64 0e80000?0e8ffff sa233 0 1 1 1 0 1 0 0 1 128/64 0e90000?0e9ffff table 2. sector address table?s29gl512n (continued) sector a24?a16 sector size (kbytes/ kwords) address range (in hexadecimal)
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 33 advance information sa234 0 1 1 1 0 1 0 1 0 128/64 0ea0000?0eaffff sa235 0 1 1 1 0 1 0 1 1 128/64 0eb0000?0ebffff sa236 0 1 1 1 0 1 1 0 0 128/64 0ec0000?0ecffff sa237 0 1 1 1 0 1 1 0 1 128/64 0ed0000?0edffff sa238 0 1 1 1 0 1 1 1 0 128/64 0ee0000?0eeffff sa239 0 1 1 1 0 1 1 1 1 128/64 0ef0000?0efffff sa240 0 1 1 1 1 0 0 0 0 128/64 0f00000?0f0ffff sa241 0 1 1 1 1 0 0 0 1 128/64 0f10000?0f1ffff sa242 0 1 1 1 1 0 0 1 0 128/64 0f20000?0f2ffff sa243 0 1 1 1 1 0 0 1 1 128/64 0f30000?0f3ffff sa244 0 1 1 1 1 0 1 0 0 128/64 0f40000?0f4ffff sa245 0 1 1 1 1 0 1 0 1 128/64 0f50000?0f5ffff sa246 0 1 1 1 1 0 1 1 0 128/64 0f60000?0f6ffff sa247 0 1 1 1 1 0 1 1 1 128/64 0f70000?0f7ffff sa248 0 1 1 1 1 1 0 0 0 128/64 0f80000?0f8ffff sa249 0 1 1 1 1 1 0 0 1 128/64 0f90000?0f9ffff sa250 0 1 1 1 1 1 0 1 0 128/64 0fa0000?0faffff sa251 0 1 1 1 1 1 0 1 1 128/64 0fb0000?0fbffff sa252 0 1 1 1 1 1 1 0 0 128/64 0fc0000?0fcffff sa253 0 1 1 1 1 1 1 0 1 128/64 0fd0000?0fdffff sa254 0 1 1 1 1 1 1 1 0 128/64 0fe0000?0feffff sa255 0 1 1 1 1 1 1 1 1 128/64 0ff0000?0ffffff sa256 1 0 0 0 0 0 0 0 0 128/64 1000000?100ffff sa257 1 0 0 0 0 0 0 0 1 128/64 1010000?101ffff sa258 1 0 0 0 0 0 0 1 0 128/64 1020000?102ffff sa259 1 0 0 0 0 0 0 1 1 128/64 1030000?103ffff sa260 1 0 0 0 0 0 1 0 0 128/64 1040000?104ffff sa261 1 0 0 0 0 0 1 0 1 128/64 1050000?105ffff sa262 1 0 0 0 0 0 1 1 0 128/64 1060000?106ffff sa263 1 0 0 0 0 0 1 1 1 128/64 1070000?107ffff sa264 1 0 0 0 0 1 0 0 0 128/64 1080000?108ffff sa265 1 0 0 0 0 1 0 0 1 128/64 1090000?109ffff sa266 1 0 0 0 0 1 0 1 0 128/64 10a0000?10affff sa267 1 0 0 0 0 1 0 1 1 128/64 10b0000?10bffff sa268 1 0 0 0 0 1 1 0 0 128/64 10c0000?10cffff table 2. sector address table?s29gl512n (continued) sector a24?a16 sector size (kbytes/ kwords) address range (in hexadecimal)
34 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information sa269 1 0 0 0 0 1 1 0 1 128/64 10d0000?10dffff sa270 1 0 0 0 0 1 1 1 0 128/64 10e0000?10effff sa271 1 0 0 0 0 1 1 1 1 128/64 10f0000?10fffff sa272 1 0 0 0 1 0 0 0 0 128/64 1100000?110ffff sa273 1 0 0 0 1 0 0 0 1 128/64 1110000?111ffff sa274 1 0 0 0 1 0 0 1 0 128/64 1120000?112ffff sa275 1 0 0 0 1 0 0 1 1 128/64 1130000?113ffff sa276 1 0 0 0 1 0 1 0 0 128/64 1140000?114ffff sa277 1 0 0 0 1 0 1 0 1 128/64 1150000?115ffff sa278 1 0 0 0 1 0 1 1 0 128/64 1160000?116ffff sa279 1 0 0 0 1 0 1 1 1 128/64 1170000?117ffff sa280 1 0 0 0 1 1 0 0 0 128/64 1180000?118ffff sa281 1 0 0 0 1 1 0 0 1 128/64 1190000?119ffff sa282 1 0 0 0 1 1 0 1 0 128/64 11a0000?11affff sa283 1 0 0 0 1 1 0 1 1 128/64 11b0000?11bffff sa284 1 0 0 0 1 1 1 0 0 128/64 11c0000?11cffff sa285 1 0 0 0 1 1 1 0 1 128/64 11d0000?11dffff sa286 1 0 0 0 1 1 1 1 0 128/64 11e0000?11effff sa287 1 0 0 0 1 1 1 1 1 128/64 11f0000?11fffff sa288 1 0 0 1 0 0 0 0 0 128/64 1200000?120ffff sa289 1 0 0 1 0 0 0 0 1 128/64 1210000?121ffff sa290 1 0 0 1 0 0 0 1 0 128/64 1220000?122ffff sa291 1 0 0 1 0 0 0 1 1 128/64 1230000?123ffff sa292 1 0 0 1 0 0 1 0 0 128/64 1240000?124ffff sa293 1 0 0 1 0 0 1 0 1 128/64 1250000?125ffff sa294 1 0 0 1 0 0 1 1 0 128/64 1260000?126ffff sa295 1 0 0 1 0 0 1 1 1 128/64 1270000?127ffff sa296 1 0 0 1 0 1 0 0 0 128/64 1280000?128ffff sa297 1 0 0 1 0 1 0 0 1 128/64 1290000?129ffff sa298 1 0 0 1 0 1 0 1 0 128/64 12a0000?12affff sa299 1 0 0 1 0 1 0 1 1 128/64 12b0000?12bffff sa300 1 0 0 1 0 1 1 0 0 128/64 12c0000?12cffff sa301 1 0 0 1 0 1 1 0 1 128/64 12d0000?12dffff sa302 1 0 0 1 0 1 1 1 0 128/64 12e0000?12effff sa303 1 0 0 1 0 1 1 1 1 128/64 12f0000?12fffff table 2. sector address table?s29gl512n (continued) sector a24?a16 sector size (kbytes/ kwords) address range (in hexadecimal)
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 35 advance information sa304 1 0 0 1 1 0 0 0 0 128/64 1300000?130ffff sa305 1 0 0 1 1 0 0 0 1 128/64 1310000?131ffff sa306 1 0 0 1 1 0 0 1 0 128/64 1320000?132ffff sa307 1 0 0 1 1 0 0 1 1 128/64 1330000?133ffff sa308 1 0 0 1 1 0 1 0 0 128/64 1340000?134ffff sa309 1 0 0 1 1 0 1 0 1 128/64 1350000?135ffff sa310 1 0 0 1 1 0 1 1 0 128/64 1360000?136ffff sa311 1 0 0 1 1 0 1 1 1 128/64 1370000?137ffff sa312 1 0 0 1 1 1 0 0 0 128/64 1380000?138ffff sa313 1 0 0 1 1 1 0 0 1 128/64 1390000?139ffff sa314 1 0 0 1 1 1 0 1 0 128/64 13a0000?13affff sa315 1 0 0 1 1 1 0 1 1 128/64 13b0000?13bffff sa316 1 0 0 1 1 1 1 0 0 128/64 13c0000?13cffff sa317 1 0 0 1 1 1 1 0 1 128/64 13d0000?13dffff sa318 1 0 0 1 1 1 1 1 0 128/64 13e0000?13effff sa319 1 0 0 1 1 1 1 1 1 128/64 13f0000?13fffff sa320 1 0 1 0 0 0 0 0 0 128/64 1400000?140ffff sa321 1 0 1 0 0 0 0 0 1 128/64 1410000?141ffff sa322 1 0 1 0 0 0 0 1 0 128/64 1420000?142ffff sa323 1 0 1 0 0 0 0 1 1 128/64 1430000?143ffff sa324 1 0 1 0 0 0 1 0 0 128/64 1440000?144ffff sa325 1 0 1 0 0 0 1 0 1 128/64 1450000?145ffff sa326 1 0 1 0 0 0 1 1 0 128/64 1460000?146ffff sa327 1 0 1 0 0 0 1 1 1 128/64 1470000?147ffff sa328 1 0 1 0 0 1 0 0 0 128/64 1480000?148ffff sa329 1 0 1 0 0 1 0 0 1 128/64 1490000?149ffff sa330 1 0 1 0 0 1 0 1 0 128/64 14a0000?14affff sa331 1 0 1 0 0 1 0 1 1 128/64 14b0000?14bffff sa332 1 0 1 0 0 1 1 0 0 128/64 14c0000?14cffff sa333 1 0 1 0 0 1 1 0 1 128/64 14d0000?14dffff sa334 1 0 1 0 0 1 1 1 0 128/64 14e0000?14effff sa335 1 0 1 0 0 1 1 1 1 128/64 14f0000?14fffff sa336 1 0 1 0 1 0 0 0 0 128/64 1500000?150ffff sa337 1 0 1 0 1 0 0 0 1 128/64 1510000?151ffff sa338 1 0 1 0 1 0 0 1 0 128/64 1520000?152ffff table 2. sector address table?s29gl512n (continued) sector a24?a16 sector size (kbytes/ kwords) address range (in hexadecimal)
36 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information sa339 1 0 1 0 1 0 0 1 1 128/64 1530000?153ffff sa340 1 0 1 0 1 0 1 0 0 128/64 1540000?154ffff sa341 1 0 1 0 1 0 1 0 1 128/64 1550000?155ffff sa342 1 0 1 0 1 0 1 1 0 128/64 1560000?156ffff sa343 1 0 1 0 1 0 1 1 1 128/64 1570000?157ffff sa344 1 0 1 0 1 1 0 0 0 128/64 1580000?158ffff sa345 1 0 1 0 1 1 0 0 1 128/64 1590000?159ffff sa346 1 0 1 0 1 1 0 1 0 128/64 15a0000?15affff sa347 1 0 1 0 1 1 0 1 1 128/64 15b0000?15bffff sa348 1 0 1 0 1 1 1 0 0 128/64 15c0000?15cffff sa349 1 0 1 0 1 1 1 0 1 128/64 15d0000?15dffff sa350 1 0 1 0 1 1 1 1 0 128/64 15e0000?15effff sa351 1 0 1 0 1 1 1 1 1 128/64 15f0000?15fffff sa352 1 0 1 1 0 0 0 0 0 128/64 1600000?160ffff sa353 1 0 1 1 0 0 0 0 1 128/64 1610000?161ffff sa354 1 0 1 1 0 0 0 1 0 128/64 1620000?162ffff sa355 1 0 1 1 0 0 0 1 1 128/64 1630000?163ffff sa356 1 0 1 1 0 0 1 0 0 128/64 1640000?164ffff sa357 1 0 1 1 0 0 1 0 1 128/64 1650000?165ffff sa358 1 0 1 1 0 0 1 1 0 128/64 1660000?166ffff sa359 1 0 1 1 0 0 1 1 1 128/64 1670000?167ffff sa360 1 0 1 1 0 1 0 0 0 128/64 1680000?168ffff sa361 1 0 1 1 0 1 0 0 1 128/64 1690000?169ffff sa362 1 0 1 1 0 1 0 1 0 128/64 16a0000?16affff sa363 1 0 1 1 0 1 0 1 1 128/64 16b0000?16bffff sa364 1 0 1 1 0 1 1 0 0 128/64 16c0000?16cffff sa365 1 0 1 1 0 1 1 0 1 128/64 16d0000?16dffff sa366 1 0 1 1 0 1 1 1 0 128/64 16e0000?16effff sa367 1 0 1 1 0 1 1 1 1 128/64 16f0000?16fffff sa368 1 0 1 1 1 0 0 0 0 128/64 1700000?170ffff sa369 1 0 1 1 1 0 0 0 1 128/64 1710000?171ffff sa370 1 0 1 1 1 0 0 1 0 128/64 1720000?172ffff sa371 1 0 1 1 1 0 0 1 1 128/64 1730000?173ffff sa372 1 0 1 1 1 0 1 0 0 128/64 1740000?174ffff sa373 1 0 1 1 1 0 1 0 1 128/64 1750000?175ffff table 2. sector address table?s29gl512n (continued) sector a24?a16 sector size (kbytes/ kwords) address range (in hexadecimal)
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 37 advance information sa374 1 0 1 1 1 0 1 1 0 128/64 1760000?176ffff sa375 1 0 1 1 1 0 1 1 1 128/64 1770000?177ffff sa376 1 0 1 1 1 1 0 0 0 128/64 1780000?178ffff sa377 1 0 1 1 1 1 0 0 1 128/64 1790000?179ffff sa378 1 0 1 1 1 1 0 1 0 128/64 17a0000?17affff sa379 1 0 1 1 1 1 0 1 1 128/64 17b0000?17bffff sa380 1 0 1 1 1 1 1 0 0 128/64 17c0000?17cffff sa381 1 0 1 1 1 1 1 0 1 128/64 17d0000?17dffff sa382 1 0 1 1 1 1 1 1 0 128/64 17e0000?17effff sa383 1 0 1 1 1 1 1 1 1 128/64 17f0000?17fffff sa384 1 1 0 0 0 0 0 0 0 128/64 1800000?180ffff sa385 1 1 0 0 0 0 0 0 1 128/64 1810000?181ffff sa386 1 1 0 0 0 0 0 1 0 128/64 1820000?182ffff sa387 1 1 0 0 0 0 0 1 1 128/64 1830000?183ffff sa388 1 1 0 0 0 0 1 0 0 128/64 1840000?184ffff sa389 1 1 0 0 0 0 1 0 1 128/64 1850000?185ffff sa390 1 1 0 0 0 0 1 1 0 128/64 1860000?186ffff sa391 1 1 0 0 0 0 1 1 1 128/64 1870000?187ffff sa392 1 1 0 0 0 1 0 0 0 128/64 1880000?188ffff sa393 1 1 0 0 0 1 0 0 1 128/64 1890000?189ffff sa394 1 1 0 0 0 1 0 1 0 128/64 18a0000?18affff sa395 1 1 0 0 0 1 0 1 1 128/64 18b0000?18bffff sa396 1 1 0 0 0 1 1 0 0 128/64 18c0000?18cffff sa397 1 1 0 0 0 1 1 0 1 128/64 18d0000?18dffff sa398 1 1 0 0 0 1 1 1 0 128/64 18e0000?18effff sa399 1 1 0 0 0 1 1 1 1 128/64 18f0000?18fffff sa400 1 1 0 0 1 0 0 0 0 128/64 1900000?190ffff sa401 1 1 0 0 1 0 0 0 1 128/64 1910000?191ffff sa402 1 1 0 0 1 0 0 1 0 128/64 1920000?192ffff sa403 1 1 0 0 1 0 0 1 1 128/64 1930000?193ffff sa404 1 1 0 0 1 0 1 0 0 128/64 1940000?194ffff sa405 1 1 0 0 1 0 1 0 1 128/64 1950000?195ffff sa406 1 1 0 0 1 0 1 1 0 128/64 1960000?196ffff sa407 1 1 0 0 1 0 1 1 1 128/64 1970000?197ffff sa408 1 1 0 0 1 1 0 0 0 128/64 1980000?198ffff table 2. sector address table?s29gl512n (continued) sector a24?a16 sector size (kbytes/ kwords) address range (in hexadecimal)
38 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information sa409 1 1 0 0 1 1 0 0 1 128/64 1990000?199ffff sa410 1 1 0 0 1 1 0 1 0 128/64 19a0000?19affff sa411 1 1 0 0 1 1 0 1 1 128/64 19b0000?19bffff sa412 1 1 0 0 1 1 1 0 0 128/64 19c0000?19cffff sa413 1 1 0 0 1 1 1 0 1 128/64 19d0000?19dffff sa414 1 1 0 0 1 1 1 1 0 128/64 19e0000?19effff sa415 1 1 0 0 1 1 1 1 1 128/64 19f0000?19fffff sa416 1 1 0 1 0 0 0 0 0 128/64 1a00000?1a0ffff sa417 1 1 0 1 0 0 0 0 1 128/64 1a10000?1a1ffff sa418 1 1 0 1 0 0 0 1 0 128/64 1a20000?1a2ffff sa419 1 1 0 1 0 0 0 1 1 128/64 1a30000?1a3ffff sa420 1 1 0 1 0 0 1 0 0 128/64 1a40000?1a4ffff sa421 1 1 0 1 0 0 1 0 1 128/64 1a50000?1a5ffff sa422 1 1 0 1 0 0 1 1 0 128/64 1a60000?1a6ffff sa423 1 1 0 1 0 0 1 1 1 128/64 1a70000?1a7ffff sa424 1 1 0 1 0 1 0 0 0 128/64 1a80000?1a8ffff sa425 1 1 0 1 0 1 0 0 1 128/64 1a90000?1a9ffff sa426 1 1 0 1 0 1 0 1 0 128/64 1aa0000?1aaffff sa427 1 1 0 1 0 1 0 1 1 128/64 1ab0000?1abffff sa428 1 1 0 1 0 1 1 0 0 128/64 1ac0000?1acffff sa429 1 1 0 1 0 1 1 0 1 128/64 1ad0000?1adffff sa430 1 1 0 1 0 1 1 1 0 128/64 1ae0000?1aeffff sa431 1 1 0 1 0 1 1 1 1 128/64 1af0000?1afffff sa432 1 1 0 1 1 0 0 0 0 128/64 1b00000?1b0ffff sa433 1 1 0 1 1 0 0 0 1 128/64 1b10000?1b1ffff sa434 1 1 0 1 1 0 0 1 0 128/64 1b20000?1b2ffff sa435 1 1 0 1 1 0 0 1 1 128/64 1b30000?1b3ffff sa436 1 1 0 1 1 0 1 0 0 128/64 1b40000?1b4ffff sa437 1 1 0 1 1 0 1 0 1 128/64 1b50000?1b5ffff sa438 1 1 0 1 1 0 1 1 0 128/64 1b60000?1b6ffff sa439 1 1 0 1 1 0 1 1 1 128/64 1b70000?1b7ffff sa440 1 1 0 1 1 1 0 0 0 128/64 1b80000?1b8ffff sa441 1 1 0 1 1 1 0 0 1 128/64 1b90000?1b9ffff sa442 1 1 0 1 1 1 0 1 0 128/64 1ba0000?1baffff sa443 1 1 0 1 1 1 0 1 1 128/64 1bb0000?1bbffff table 2. sector address table?s29gl512n (continued) sector a24?a16 sector size (kbytes/ kwords) address range (in hexadecimal)
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 39 advance information sa444 1 1 0 1 1 1 1 0 0 128/64 1bc0000?1bcffff sa445 1 1 0 1 1 1 1 0 1 128/64 1bd0000?1bdffff sa446 1 1 0 1 1 1 1 1 0 128/64 1be0000?1beffff sa447 1 1 0 1 1 1 1 1 1 128/64 1bf0000?1bfffff sa448 1 1 1 0 0 0 0 0 0 128/64 1c00000?1c0ffff sa449 1 1 1 0 0 0 0 0 1 128/64 1c10000?1c1ffff sa450 1 1 1 0 0 0 0 1 0 128/64 1c20000?1c2ffff sa451 1 1 1 0 0 0 0 1 1 128/64 1c30000?1c3ffff sa452 1 1 1 0 0 0 1 0 0 128/64 1c40000?1c4ffff sa453 1 1 1 0 0 0 1 0 1 128/64 1c50000?1c5ffff sa454 1 1 1 0 0 0 1 1 0 128/64 1c60000?1c6ffff sa455 1 1 1 0 0 0 1 1 1 128/64 1c70000?1c7ffff sa456 1 1 1 0 0 1 0 0 0 128/64 1c80000?1c8ffff sa457 1 1 1 0 0 1 0 0 1 128/64 1c90000?1c9ffff sa458 1 1 1 0 0 1 0 1 0 128/64 1ca0000?1caffff sa459 1 1 1 0 0 1 0 1 1 128/64 1cb0000?1cbffff sa460 1 1 1 0 0 1 1 0 0 128/64 1cc0000?1ccffff sa461 1 1 1 0 0 1 1 0 1 128/64 1cd0000?1cdffff sa462 1 1 1 0 0 1 1 1 0 128/64 1ce0000?1ceffff sa463 1 1 1 0 0 1 1 1 1 128/64 1cf0000?1cfffff sa464 1 1 1 0 1 0 0 0 0 128/64 1d00000?1d0ffff sa465 1 1 1 0 1 0 0 0 1 128/64 1d10000?1d1ffff sa466 1 1 1 0 1 0 0 1 0 128/64 1d20000?1d2ffff sa467 1 1 1 0 1 0 0 1 1 128/64 1d30000?1d3ffff sa468 1 1 1 0 1 0 1 0 0 128/64 1d40000?1d4ffff sa469 1 1 1 0 1 0 1 0 1 128/64 1d50000?1d5ffff sa470 1 1 1 0 1 0 1 1 0 128/64 1d60000?1d6ffff sa471 1 1 1 0 1 0 1 1 1 128/64 1d70000?1d7ffff sa472 1 1 1 0 1 1 0 0 0 128/64 1d80000?1d8ffff sa473 1 1 1 0 1 1 0 0 1 128/64 1d90000?1d9ffff sa474 1 1 1 0 1 1 0 1 0 128/64 1da0000?1daffff sa475 1 1 1 0 1 1 0 1 1 128/64 1db0000?1dbffff sa476 1 1 1 0 1 1 1 0 0 128/64 1dc0000?1dcffff sa477 1 1 1 0 1 1 1 0 1 128/64 1dd0000?1ddffff sa478 1 1 1 0 1 1 1 1 0 128/64 1de0000?1deffff table 2. sector address table?s29gl512n (continued) sector a24?a16 sector size (kbytes/ kwords) address range (in hexadecimal)
40 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information sa479 1 1 1 0 1 1 1 1 1 128/64 1df0000?1dfffff sa480 1 1 1 1 0 0 0 0 0 128/64 1e00000?1e0ffff sa481 1 1 1 1 0 0 0 0 1 128/64 1e10000?1e1ffff sa482 1 1 1 1 0 0 0 1 0 128/64 1e20000?1e2ffff sa483 1 1 1 1 0 0 0 1 1 128/64 1e30000?1e3ffff sa484 1 1 1 1 0 0 1 0 0 128/64 1e40000?1e4ffff sa485 1 1 1 1 0 0 1 0 1 128/64 1e50000?1e5ffff sa486 1 1 1 1 0 0 1 1 0 128/64 1e60000?1e6ffff sa487 1 1 1 1 0 0 1 1 1 128/64 1e70000?1e7ffff sa488 1 1 1 1 0 1 0 0 0 128/64 1e80000?1e8ffff sa489 1 1 1 1 0 1 0 0 1 128/64 1e90000?1e9ffff sa490 1 1 1 1 0 1 0 1 0 128/64 1ea0000?1eaffff sa491 1 1 1 1 0 1 0 1 1 128/64 1eb0000?1ebffff sa492 1 1 1 1 0 1 1 0 0 128/64 1ec0000?1ecffff sa493 1 1 1 1 0 1 1 0 1 128/64 1ed0000?1edffff sa494 1 1 1 1 0 1 1 1 0 128/64 1ee0000?1eeffff sa495 1 1 1 1 0 1 1 1 1 128/64 1ef0000?1efffff sa496 1 1 1 1 1 0 0 0 0 128/64 1f00000?1f0ffff sa497 1 1 1 1 1 0 0 0 1 128/64 1f10000?1f1ffff sa498 1 1 1 1 1 0 0 1 0 128/64 1f20000?1f2ffff sa499 1 1 1 1 1 0 0 1 1 128/64 1f30000?1f3ffff sa500 1 1 1 1 1 0 1 0 0 128/64 1f40000?1f4ffff sa501 1 1 1 1 1 0 1 0 1 128/64 1f50000?1f5ffff sa502 1 1 1 1 1 0 1 1 0 128/64 1f60000?1f6ffff sa503 1 1 1 1 1 0 1 1 1 128/64 1f70000?1f7ffff sa504 1 1 1 1 1 1 0 0 0 128/64 1f80000?1f8ffff sa505 1 1 1 1 1 1 0 0 1 128/64 1f90000?1f9ffff sa506 1 1 1 1 1 1 0 1 0 128/64 1fa0000?1faffff sa507 1 1 1 1 1 1 0 1 1 128/64 1fb0000?1fbffff sa508 1 1 1 1 1 1 1 0 0 128/64 1fc0000?1fcffff sa509 1 1 1 1 1 1 1 0 1 128/64 1fd0000?1fdffff sa510 1 1 1 1 1 1 1 1 0 128/64 1fe0000?1feffff sa511 1 1 1 1 1 1 1 1 1 128/64 1ff0000?1ffffff table 2. sector address table?s29gl512n (continued) sector a24?a16 sector size (kbytes/ kwords) address range (in hexadecimal)
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 41 advance information ta b l e 3 . sector address table?s29gl256n sector a23?a16 sector size (kbytes/ kwords) address range (in hexadecimal) sa0 0 0 0 0 0 0 0 0 128/64 0000000?000ffff sa1 0 0 0 0 0 0 0 1 128/64 0010000?001ffff sa2 0 0 0 0 0 0 1 0 128/64 0020000?002ffff sa3 0 0 0 0 0 0 1 1 128/64 0030000?003ffff sa4 0 0 0 0 0 1 0 0 128/64 0040000?004ffff sa5 0 0 0 0 0 1 0 1 128/64 0050000?005ffff sa6 0 0 0 0 0 1 1 0 128/64 0060000?006ffff sa7 0 0 0 0 0 1 1 1 128/64 0070000?007ffff sa8 0 0 0 0 1 0 0 0 128/64 0080000?008ffff sa9 0 0 0 0 1 0 0 1 128/64 0090000?009ffff sa10 0 0 0 0 1 0 1 0 128/64 00a0000?00affff sa11 0 0 0 0 1 0 1 1 128/64 00b0000?00bffff sa12 0 0 0 0 1 1 0 0 128/64 00c0000?00cffff sa13 0 0 0 0 1 1 0 1 128/64 00d0000?00dffff sa14 0 0 0 0 1 1 1 0 128/64 00e0000?00effff sa15 0 0 0 0 1 1 1 1 128/64 00f0000?00fffff sa16 0 0 0 1 0 0 0 0 128/64 0100000?010ffff sa17 0 0 0 1 0 0 0 1 128/64 0110000?011ffff sa18 0 0 0 1 0 0 1 0 128/64 0120000?012ffff sa19 0 0 0 1 0 0 1 1 128/64 0130000?013ffff sa20 0 0 0 1 0 1 0 0 128/64 0140000?014ffff sa21 0 0 0 1 0 1 0 1 128/64 0150000?015ffff sa22 0 0 0 1 0 1 1 0 128/64 0160000?016ffff sa23 0 0 0 1 0 1 1 1 128/64 0170000?017ffff sa24 0 0 0 1 1 0 0 0 128/64 0180000?018ffff sa25 0 0 0 1 1 0 0 1 128/64 0190000?019ffff sa26 0 0 0 1 1 0 1 0 128/64 01a0000?01affff sa27 0 0 0 1 1 0 1 1 128/64 01b0000?01bffff sa28 0 0 0 1 1 1 0 0 128/64 01c0000?01cffff sa29 0 0 0 1 1 1 0 1 128/64 01d0000?01dffff sa30 0 0 0 1 1 1 1 0 128/64 01e0000?01effff sa31 0 0 0 1 1 1 1 1 128/64 01f0000?01fffff sa32 0 0 1 0 0 0 0 0 128/64 0200000?020ffff sa33 0 0 1 0 0 0 0 1 128/64 0210000?021ffff
42 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information sa34 0 0 1 0 0 0 1 0 128/64 0220000?022ffff sa35 0 0 1 0 0 0 1 1 128/64 0230000?023ffff sa36 0 0 1 0 0 1 0 0 128/64 0240000?024ffff sa37 0 0 1 0 0 1 0 1 128/64 0250000?025ffff sa38 0 0 1 0 0 1 1 0 128/64 0260000?026ffff sa39 0 0 1 0 0 1 1 1 128/64 0270000?027ffff sa40 0 0 1 0 1 0 0 0 128/64 0280000?028ffff sa41 0 0 1 0 1 0 0 1 128/64 0290000?029ffff sa42 0 0 1 0 1 0 1 0 128/64 02a0000?02affff sa43 0 0 1 0 1 0 1 1 128/64 02b0000?02bffff sa44 0 0 1 0 1 1 0 0 128/64 02c0000?02cffff sa45 0 0 1 0 1 1 0 1 128/64 02d0000?02dffff sa46 0 0 1 0 1 1 1 0 128/64 02e0000?02effff sa47 0 0 1 0 1 1 1 1 128/64 02f0000?02fffff sa48 0 0 1 1 0 0 0 0 128/64 0300000?030ffff sa49 0 0 1 1 0 0 0 1 128/64 0310000?031ffff sa50 0 0 1 1 0 0 1 0 128/64 0320000?032ffff sa51 0 0 1 1 0 0 1 1 128/64 0330000?033ffff sa52 0 0 1 1 0 1 0 0 128/64 0340000?034ffff sa53 0 0 1 1 0 1 0 1 128/64 0350000?035ffff sa54 0 0 1 1 0 1 1 0 128/64 0360000?036ffff sa55 0 0 1 1 0 1 1 1 128/64 0370000?037ffff sa56 0 0 1 1 1 0 0 0 128/64 0380000?038ffff sa57 0 0 1 1 1 0 0 1 128/64 0390000?039ffff sa58 0 0 1 1 1 0 1 0 128/64 03a0000?03affff sa59 0 0 1 1 1 0 1 1 128/64 03b0000?03bffff sa60 0 0 1 1 1 1 0 0 128/64 03c0000?03cffff sa61 0 0 1 1 1 1 0 1 128/64 03d0000?03dffff sa62 0 0 1 1 1 1 1 0 128/64 03e0000?03effff sa63 0 0 1 1 1 1 1 1 128/64 03f0000?03fffff sa64 0 1 0 0 0 0 0 0 128/64 0400000?040ffff sa65 0 1 0 0 0 0 0 1 128/64 0410000?041ffff sa66 0 1 0 0 0 0 1 0 128/64 0420000?042ffff sa67 0 1 0 0 0 0 1 1 128/64 0430000?043ffff sa68 0 1 0 0 0 1 0 0 128/64 0440000?044ffff table 3. sector address table?s29gl256n (continued) sector a23?a16 sector size (kbytes/ kwords) address range (in hexadecimal)
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 43 advance information sa69 0 1 0 0 0 1 0 1 128/64 0450000?045ffff sa70 0 1 0 0 0 1 1 0 128/64 0460000?046ffff sa71 0 1 0 0 0 1 1 1 128/64 0470000?047ffff sa72 0 1 0 0 1 0 0 0 128/64 0480000?048ffff sa73 0 1 0 0 1 0 0 1 128/64 0490000?049ffff sa74 0 1 0 0 1 0 1 0 128/64 04a0000?04affff sa75 0 1 0 0 1 0 1 1 128/64 04b0000?04bffff sa76 0 1 0 0 1 1 0 0 128/64 04c0000?04cffff sa77 0 1 0 0 1 1 0 1 128/64 04d0000?04dffff sa78 0 1 0 0 1 1 1 0 128/64 04e0000?04effff sa79 0 1 0 0 1 1 1 1 128/64 04f0000?04fffff sa80 0 1 0 1 0 0 0 0 128/64 0500000?050ffff sa81 0 1 0 1 0 0 0 1 128/64 0510000?051ffff sa82 0 1 0 1 0 0 1 0 128/64 0520000?052ffff sa83 0 1 0 1 0 0 1 1 128/64 0530000?053ffff sa84 0 1 0 1 0 1 0 0 128/64 0540000?054ffff sa85 0 1 0 1 0 1 0 1 128/64 0550000?055ffff sa86 0 1 0 1 0 1 1 0 128/64 0560000?056ffff sa87 0 1 0 1 0 1 1 1 128/64 0570000?057ffff sa88 0 1 0 1 1 0 0 0 128/64 0580000?058ffff sa89 0 1 0 1 1 0 0 1 128/64 0590000?059ffff sa90 0 1 0 1 1 0 1 0 128/64 05a0000?05affff sa91 0 1 0 1 1 0 1 1 128/64 05b0000?05bffff sa92 0 1 0 1 1 1 0 0 128/64 05c0000?05cffff sa93 0 1 0 1 1 1 0 1 128/64 05d0000?05dffff sa94 0 1 0 1 1 1 1 0 128/64 05e0000?05effff sa95 0 1 0 1 1 1 1 1 128/64 05f0000?05fffff sa96 0 1 1 0 0 0 0 0 128/64 0600000?060ffff sa97 0 1 1 0 0 0 0 1 128/64 0610000?061ffff sa98 0 1 1 0 0 0 1 0 128/64 0620000?062ffff sa99 0 1 1 0 0 0 1 1 128/64 0630000?063ffff sa100 0 1 1 0 0 1 0 0 128/64 0640000?064ffff sa101 0 1 1 0 0 1 0 1 128/64 0650000?065ffff sa102 0 1 1 0 0 1 1 0 128/64 0660000?066ffff sa103 0 1 1 0 0 1 1 1 128/64 0670000?067ffff table 3. sector address table?s29gl256n (continued) sector a23?a16 sector size (kbytes/ kwords) address range (in hexadecimal)
44 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information sa104 0 1 1 0 1 0 0 0 128/64 0680000?068ffff sa105 0 1 1 0 1 0 0 1 128/64 0690000?069ffff sa106 0 1 1 0 1 0 1 0 128/64 06a0000?06affff sa107 0 1 1 0 1 0 1 1 128/64 06b0000?06bffff sa108 0 1 1 0 1 1 0 0 128/64 06c0000?06cffff sa109 0 1 1 0 1 1 0 1 128/64 06d0000?06dffff sa110 0 1 1 0 1 1 1 0 128/64 06e0000?06effff sa111 0 1 1 0 1 1 1 1 128/64 06f0000?06fffff sa112 0 1 1 1 0 0 0 0 128/64 0700000?070ffff sa113 0 1 1 1 0 0 0 1 128/64 0710000?071ffff sa114 0 1 1 1 0 0 1 0 128/64 0720000?072ffff sa115 0 1 1 1 0 0 1 1 128/64 0730000?073ffff sa116 0 1 1 1 0 1 0 0 128/64 0740000?074ffff sa117 0 1 1 1 0 1 0 1 128/64 0750000?075ffff sa118 0 1 1 1 0 1 1 0 128/64 0760000?076ffff sa119 0 1 1 1 0 1 1 1 128/64 0770000?077ffff sa120 0 1 1 1 1 0 0 0 128/64 0780000?078ffff sa121 0 1 1 1 1 0 0 1 128/64 0790000?079ffff sa122 0 1 1 1 1 0 1 0 128/64 07a0000?07affff sa123 0 1 1 1 1 0 1 1 128/64 07b0000?07bffff sa124 0 1 1 1 1 1 0 0 128/64 07c0000?07cffff sa125 0 1 1 1 1 1 0 1 128/64 07d0000?07dffff sa126 0 1 1 1 1 1 1 0 128/64 07e0000?07effff sa127 0 1 1 1 1 1 1 1 128/64 07f0000?07fffff sa128 1 0 0 0 0 0 0 0 128/64 0800000?080ffff sa129 1 0 0 0 0 0 0 1 128/64 0810000?081ffff sa130 1 0 0 0 0 0 1 0 128/64 0820000?082ffff sa131 1 0 0 0 0 0 1 1 128/64 0830000?083ffff sa132 1 0 0 0 0 1 0 0 128/64 0840000?084ffff sa133 1 0 0 0 0 1 0 1 128/64 0850000?085ffff sa134 1 0 0 0 0 1 1 0 128/64 0860000?086ffff sa135 1 0 0 0 0 1 1 1 128/64 0870000?087ffff sa136 1 0 0 0 1 0 0 0 128/64 0880000?088ffff sa137 1 0 0 0 1 0 0 1 128/64 0890000?089ffff sa138 1 0 0 0 1 0 1 0 128/64 08a0000?08affff table 3. sector address table?s29gl256n (continued) sector a23?a16 sector size (kbytes/ kwords) address range (in hexadecimal)
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 45 advance information sa139 1 0 0 0 1 0 1 1 128/64 08b0000?08bffff sa140 1 0 0 0 1 1 0 0 128/64 08c0000?08cffff sa141 1 0 0 0 1 1 0 1 128/64 08d0000?08dffff sa142 1 0 0 0 1 1 1 0 128/64 08e0000?08effff sa143 1 0 0 0 1 1 1 1 128/64 08f0000?08fffff sa144 1 0 0 1 0 0 0 0 128/64 0900000?090ffff sa145 1 0 0 1 0 0 0 1 128/64 0910000?091ffff sa146 1 0 0 1 0 0 1 0 128/64 0920000?092ffff sa147 1 0 0 1 0 0 1 1 128/64 0930000?093ffff sa148 1 0 0 1 0 1 0 0 128/64 0940000?094ffff sa149 1 0 0 1 0 1 0 1 128/64 0950000?095ffff sa150 1 0 0 1 0 1 1 0 128/64 0960000?096ffff sa151 1 0 0 1 0 1 1 1 128/64 0970000?097ffff sa152 1 0 0 1 1 0 0 0 128/64 0980000?098ffff sa153 1 0 0 1 1 0 0 1 128/64 0990000?099ffff sa154 1 0 0 1 1 0 1 0 128/64 09a0000?09affff sa155 1 0 0 1 1 0 1 1 128/64 09b0000?09bffff sa156 1 0 0 1 1 1 0 0 128/64 09c0000?09cffff sa157 1 0 0 1 1 1 0 1 128/64 09d0000?09dffff sa158 1 0 0 1 1 1 1 0 128/64 09e0000?09effff sa159 1 0 0 1 1 1 1 1 128/64 09f0000?09fffff sa160 1 0 1 0 0 0 0 0 128/64 0a00000?0a0ffff sa161 1 0 1 0 0 0 0 1 128/64 0a10000?0a1ffff sa162 1 0 1 0 0 0 1 0 128/64 0a20000?0a2ffff sa163 1 0 1 0 0 0 1 1 128/64 0a30000?0a3ffff sa164 1 0 1 0 0 1 0 0 128/64 0a40000?0a4ffff sa165 1 0 1 0 0 1 0 1 128/64 0a50000?0a5ffff sa166 1 0 1 0 0 1 1 0 128/64 0a60000?0a6ffff sa167 1 0 1 0 0 1 1 1 128/64 0a70000?0a7ffff sa168 1 0 1 0 1 0 0 0 128/64 0a80000?0a8ffff sa169 1 0 1 0 1 0 0 1 128/64 0a90000?0a9ffff sa170 1 0 1 0 1 0 1 0 128/64 0aa0000?0aaffff sa171 1 0 1 0 1 0 1 1 128/64 0ab0000?0abffff sa172 1 0 1 0 1 1 0 0 128/64 0ac0000?0acffff sa173 1 0 1 0 1 1 0 1 128/64 0ad0000?0adffff table 3. sector address table?s29gl256n (continued) sector a23?a16 sector size (kbytes/ kwords) address range (in hexadecimal)
46 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information sa174 1 0 1 0 1 1 1 0 128/64 0ae0000?0aeffff sa175 1 0 1 0 1 1 1 1 128/64 0af0000?0afffff sa176 1 0 1 1 0 0 0 0 128/64 0b00000?0b0ffff sa177 1 0 1 1 0 0 0 1 128/64 0b10000?0b1ffff sa178 1 0 1 1 0 0 1 0 128/64 0b20000?0b2ffff sa179 1 0 1 1 0 0 1 1 128/64 0b30000?0b3ffff sa180 1 0 1 1 0 1 0 0 128/64 0b40000?0b4ffff sa181 1 0 1 1 0 1 0 1 128/64 0b50000?0b5ffff sa182 1 0 1 1 0 1 1 0 128/64 0b60000?0b6ffff sa183 1 0 1 1 0 1 1 1 128/64 0b70000?0b7ffff sa184 1 0 1 1 1 0 0 0 128/64 0b80000?0b8ffff sa185 1 0 1 1 1 0 0 1 128/64 0b90000?0b9ffff sa186 1 0 1 1 1 0 1 0 128/64 0ba0000?0baffff sa187 1 0 1 1 1 0 1 1 128/64 0bb0000?0bbffff sa188 1 0 1 1 1 1 0 0 128/64 0bc0000?0bcffff sa189 1 0 1 1 1 1 0 1 128/64 0bd0000?0bdffff sa190 1 0 1 1 1 1 1 0 128/64 0be0000?0beffff sa191 1 0 1 1 1 1 1 1 128/64 0bf0000?0bfffff sa192 1 1 0 0 0 0 0 0 128/64 0c00000?0c0ffff sa193 1 1 0 0 0 0 0 1 128/64 0c10000?0c1ffff sa194 1 1 0 0 0 0 1 0 128/64 0c20000?0c2ffff sa195 1 1 0 0 0 0 1 1 128/64 0c30000?0c3ffff sa196 1 1 0 0 0 1 0 0 128/64 0c40000?0c4ffff sa197 1 1 0 0 0 1 0 1 128/64 0c50000?0c5ffff sa198 1 1 0 0 0 1 1 0 128/64 0c60000?0c6ffff sa199 1 1 0 0 0 1 1 1 128/64 0c70000?0c7ffff sa200 1 1 0 0 1 0 0 0 128/64 0c80000?0c8ffff sa201 1 1 0 0 1 0 0 1 128/64 0c90000?0c9ffff sa202 1 1 0 0 1 0 1 0 128/64 0ca0000?0caffff sa203 1 1 0 0 1 0 1 1 128/64 0cb0000?0cbffff sa204 1 1 0 0 1 1 0 0 128/64 0cc0000?0ccffff sa205 1 1 0 0 1 1 0 1 128/64 0cd0000?0cdffff sa206 1 1 0 0 1 1 1 0 128/64 0ce0000?0ceffff sa207 1 1 0 0 1 1 1 1 128/64 0cf0000?0cfffff sa208 1 1 0 1 0 0 0 0 128/64 0d00000?0d0ffff table 3. sector address table?s29gl256n (continued) sector a23?a16 sector size (kbytes/ kwords) address range (in hexadecimal)
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 47 advance information sa209 1 1 0 1 0 0 0 1 128/64 0d10000?0d1ffff sa210 1 1 0 1 0 0 1 0 128/64 0d20000?0d2ffff sa211 1 1 0 1 0 0 1 1 128/64 0d30000?0d3ffff sa212 1 1 0 1 0 1 0 0 128/64 0d40000?0d4ffff sa213 1 1 0 1 0 1 0 1 128/64 0d50000?0d5ffff sa214 1 1 0 1 0 1 1 0 128/64 0d60000?0d6ffff sa215 1 1 0 1 0 1 1 1 128/64 0d70000?0d7ffff sa216 1 1 0 1 1 0 0 0 128/64 0d80000?0d8ffff sa217 1 1 0 1 1 0 0 1 128/64 0d90000?0d9ffff sa218 1 1 0 1 1 0 1 0 128/64 0da0000?0daffff sa219 1 1 0 1 1 0 1 1 128/64 0db0000?0dbffff sa220 1 1 0 1 1 1 0 0 128/64 0dc0000?0dcffff sa221 1 1 0 1 1 1 0 1 128/64 0dd0000?0ddffff sa222 1 1 0 1 1 1 1 0 128/64 0de0000?0deffff sa223 1 1 0 1 1 1 1 1 128/64 0df0000?0dfffff sa224 1 1 1 0 0 0 0 0 128/64 0e00000?0e0ffff sa225 1 1 1 0 0 0 0 1 128/64 0e10000?0e1ffff sa226 1 1 1 0 0 0 1 0 128/64 0e20000?0e2ffff sa227 1 1 1 0 0 0 1 1 128/64 0e30000?0e3ffff sa228 1 1 1 0 0 1 0 0 128/64 0e40000?0e4ffff sa229 1 1 1 0 0 1 0 1 128/64 0e50000?0e5ffff sa230 1 1 1 0 0 1 1 0 128/64 0e60000?0e6ffff sa231 1 1 1 0 0 1 1 1 128/64 0e70000?0e7ffff sa232 1 1 1 0 1 0 0 0 128/64 0e80000?0e8ffff sa233 1 1 1 0 1 0 0 1 128/64 0e90000?0e9ffff sa234 1 1 1 0 1 0 1 0 128/64 0ea0000?0eaffff sa235 1 1 1 0 1 0 1 1 128/64 0eb0000?0ebffff sa236 1 1 1 0 1 1 0 0 128/64 0ec0000?0ecffff sa237 1 1 1 0 1 1 0 1 128/64 0ed0000?0edffff sa238 1 1 1 0 1 1 1 0 128/64 0ee0000?0eeffff sa239 1 1 1 0 1 1 1 1 128/64 0ef0000?0efffff sa240 1 1 1 1 0 0 0 0 128/64 0f00000?0f0ffff sa241 1 1 1 1 0 0 0 1 128/64 0f10000?0f1ffff sa242 1 1 1 1 0 0 1 0 128/64 0f20000?0f2ffff sa243 1 1 1 1 0 0 1 1 128/64 0f30000?0f3ffff table 3. sector address table?s29gl256n (continued) sector a23?a16 sector size (kbytes/ kwords) address range (in hexadecimal)
48 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information sa244 1 1 1 1 0 1 0 0 128/64 0f40000?0f4ffff sa245 1 1 1 1 0 1 0 1 128/64 0f50000?0f5ffff sa246 1 1 1 1 0 1 1 0 128/64 0f60000?0f6ffff sa247 1 1 1 1 0 1 1 1 128/64 0f70000?0f7ffff sa248 1 1 1 1 1 0 0 0 128/64 0f80000?0f8ffff sa249 1 1 1 1 1 0 0 1 128/64 0f90000?0f9ffff sa250 1 1 1 1 1 0 1 0 128/64 0fa0000?0faffff sa251 1 1 1 1 1 0 1 1 128/64 0fb0000?0fbffff sa252 1 1 1 1 1 1 0 0 128/64 0fc0000?0fcffff sa253 1 1 1 1 1 1 0 1 128/64 0fd0000?0fdffff sa254 1 1 1 1 1 1 1 0 128/64 0fe0000?0feffff sa255 1 1 1 1 1 1 1 1 128/64 0ff0000?0ffffff ta b l e 4 . sector address table?s29gl128n sector a22?a16 sector size (kbytes/ kwords) address range (in hexadecimal) sa0 0 0 0 0 0 0 128/64 0000000?000ffff sa1 0 0 0 0 0 1 128/64 0010000?001ffff sa2 0 0 0 0 1 0 128/64 0020000?002ffff sa3 0 0 0 0 1 1 128/64 0030000?003ffff sa4 0 0 0 1 0 0 128/64 0040000?004ffff sa5 0 0 0 1 0 1 128/64 0050000?005ffff sa6 0 0 0 1 1 0 128/64 0060000?006ffff sa7 0 0 0 1 1 1 128/64 0070000?007ffff sa8 0 0 1 0 0 0 128/64 0080000?008ffff sa9 0 0 1 0 0 1 128/64 0090000?009ffff sa10 0 0 1 0 1 0 128/64 00a0000?00affff sa11 0 0 1 0 1 1 128/64 00b0000?00bffff sa12 0 0 1 1 0 0 128/64 00c0000?00cffff sa13 0 0 1 1 0 1 128/64 00d0000?00dffff sa14 0 0 1 1 1 0 128/64 00e0000?00effff sa15 0 0 1 1 1 1 128/64 00f0000?00fffff sa16 0 1 0 0 0 0 128/64 0100000?010ffff sa17 0 1 0 0 0 1 128/64 0110000?011ffff table 3. sector address table?s29gl256n (continued) sector a23?a16 sector size (kbytes/ kwords) address range (in hexadecimal)
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 49 advance information sa18 0 1 0 0 1 0 128/64 0120000?012ffff sa19 0 1 0 0 1 1 128/64 0130000?013ffff sa20 0 1 0 1 0 0 128/64 0140000?014ffff sa21 0 1 0 1 0 1 128/64 0150000?015ffff sa22 0 1 0 1 1 0 128/64 0160000?016ffff sa23 0 1 0 1 1 1 128/64 0170000?017ffff sa24 0 1 1 0 0 0 128/64 0180000?018ffff sa25 0 1 1 0 0 1 128/64 0190000?019ffff sa26 0 1 1 0 1 0 128/64 01a0000?01affff sa27 0 1 1 0 1 1 128/64 01b0000?01bffff sa28 0 1 1 1 0 0 128/64 01c0000?01cffff sa29 0 1 1 1 0 1 128/64 01d0000?01dffff sa30 0 1 1 1 1 0 128/64 01e0000?01effff sa31 0 1 1 1 1 1 128/64 01f0000?01fffff sa32 1 0 0 0 0 0 128/64 0200000?020ffff sa33 1 0 0 0 0 1 128/64 0210000?021ffff sa34 1 0 0 0 1 0 128/64 0220000?022ffff sa35 1 0 0 0 1 1 128/64 0230000?023ffff sa36 1 0 0 1 0 0 128/64 0240000?024ffff sa37 1 0 0 1 0 1 128/64 0250000?025ffff sa38 1 0 0 1 1 0 128/64 0260000?026ffff sa39 1 0 0 1 1 1 128/64 0270000?027ffff sa40 1 0 1 0 0 0 128/64 0280000?028ffff sa41 1 0 1 0 0 1 128/64 0290000?029ffff sa42 1 0 1 0 1 0 128/64 02a0000?02affff sa43 1 0 1 0 1 1 128/64 02b0000?02bffff sa44 1 0 1 1 0 0 128/64 02c0000?02cffff sa45 1 0 1 1 0 1 128/64 02d0000?02dffff sa46 1 0 1 1 1 0 128/64 02e0000?02effff sa47 1 0 1 1 1 1 128/64 02f0000?02fffff sa48 1 1 0 0 0 0 128/64 0300000?030ffff sa49 1 1 0 0 0 1 128/64 0310000?031ffff sa50 1 1 0 0 1 0 128/64 0320000?032ffff sa51 1 1 0 0 1 1 128/64 0330000?033ffff sa52 1 1 0 1 0 0 128/64 0340000?034ffff table 4. sector address table?s29gl128n (continued) sector a22?a16 sector size (kbytes/ kwords) address range (in hexadecimal)
50 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information sa53 1 1 0 1 0 1 128/64 0350000?035ffff sa54 1 1 0 1 1 0 128/64 0360000?036ffff sa55 1 1 0 1 1 1 128/64 0370000?037ffff sa56 1 1 1 0 0 0 128/64 0380000?038ffff sa57 1 1 1 0 0 1 128/64 0390000?039ffff sa58 1 1 1 0 1 0 128/64 03a0000?03affff sa59 1 1 1 0 1 1 128/64 03b0000?03bffff sa60 1 1 1 1 0 0 128/64 03c0000?03cffff sa61 1 1 1 1 0 1 128/64 03d0000?03dffff sa62 1 1 1 1 1 0 128/64 03e0000?03effff sa63 1 1 1 1 1 1 128/64 03f0000?03fffff sa64 0 0 0 0 0 0 128/64 0400000?040ffff sa65 0 0 0 0 0 1 128/64 0410000?041ffff sa66 0 0 0 0 1 0 128/64 0420000?042ffff sa67 0 0 0 0 1 1 128/64 0430000?043ffff sa68 0 0 0 1 0 0 128/64 0440000?044ffff sa69 0 0 0 1 0 1 128/64 0450000?045ffff sa70 0 0 0 1 1 0 128/64 0460000?046ffff sa71 0 0 0 1 1 1 128/64 0470000?047ffff sa72 0 0 1 0 0 0 128/64 0480000?048ffff sa73 0 0 1 0 0 1 128/64 0490000?049ffff sa74 0 0 1 0 1 0 128/64 04a0000?04affff sa75 0 0 1 0 1 1 128/64 04b0000?04bffff sa76 0 0 1 1 0 0 128/64 04c0000?04cffff sa77 0 0 1 1 0 1 128/64 04d0000?04dffff sa78 0 0 1 1 1 0 128/64 04e0000?04effff sa79 0 0 1 1 1 1 128/64 04f0000?04fffff sa80 0 1 0 0 0 0 128/64 0500000?050ffff sa81 0 1 0 0 0 1 128/64 0510000?051ffff sa82 0 1 0 0 1 0 128/64 0520000?052ffff sa83 0 1 0 0 1 1 128/64 0530000?053ffff sa84 0 1 0 1 0 0 128/64 0540000?054ffff sa85 0 1 0 1 0 1 128/64 0550000?055ffff sa86 0 1 0 1 1 0 128/64 0560000?056ffff sa87 0 1 0 1 1 1 128/64 0570000?057ffff table 4. sector address table?s29gl128n (continued) sector a22?a16 sector size (kbytes/ kwords) address range (in hexadecimal)
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 51 advance information sa88 0 1 1 0 0 0 128/64 0580000?058ffff sa89 0 1 1 0 0 1 128/64 0590000?059ffff sa90 0 1 1 0 1 0 128/64 05a0000?05affff sa91 0 1 1 0 1 1 128/64 05b0000?05bffff sa92 0 1 1 1 0 0 128/64 05c0000?05cffff sa93 0 1 1 1 0 1 128/64 05d0000?05dffff sa94 0 1 1 1 1 0 128/64 05e0000?05effff sa95 0 1 1 1 1 1 128/64 05f0000?05fffff sa96 1 0 0 0 0 0 128/64 0600000?060ffff sa97 1 0 0 0 0 1 128/64 0610000?061ffff sa98 1 0 0 0 1 0 128/64 0620000?062ffff sa99 1 0 0 0 1 1 128/64 0630000?063ffff sa100 1 0 0 1 0 0 128/64 0640000?064ffff sa101 1 0 0 1 0 1 128/64 0650000?065ffff sa102 1 0 0 1 1 0 128/64 0660000?066ffff sa103 1 0 0 1 1 1 128/64 0670000?067ffff sa104 1 0 1 0 0 0 128/64 0680000?068ffff sa105 1 0 1 0 0 1 128/64 0690000?069ffff sa106 1 0 1 0 1 0 128/64 06a0000?06affff sa107 1 0 1 0 1 1 128/64 06b0000?06bffff sa108 1 0 1 1 0 0 128/64 06c0000?06cffff sa109 1 0 1 1 0 1 128/64 06d0000?06dffff sa110 1 0 1 1 1 0 128/64 06e0000?06effff sa111 1 0 1 1 1 1 128/64 06f0000?06fffff sa112 1 1 0 0 0 0 128/64 0700000?070ffff sa113 1 1 0 0 0 1 128/64 0710000?071ffff sa114 1 1 0 0 1 0 128/64 0720000?072ffff sa115 1 1 0 0 1 1 128/64 0730000?073ffff sa116 1 1 0 1 0 0 128/64 0740000?074ffff sa117 1 1 0 1 0 1 128/64 0750000?075ffff sa118 1 1 0 1 1 0 128/64 0760000?076ffff sa119 1 1 0 1 1 1 128/64 0770000?077ffff sa120 1 1 1 0 0 0 128/64 0780000?078ffff sa121 1 1 1 0 0 1 128/64 0790000?079ffff sa122 1 1 1 0 1 0 128/64 07a0000?07affff table 4. sector address table?s29gl128n (continued) sector a22?a16 sector size (kbytes/ kwords) address range (in hexadecimal)
52 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information autoselect mode the autoselect mode provides manufacturer and device identification, and sector group protection verification, through identifier codes output on dq7?dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. how- ever, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires vid on ad- dress pin a9. address pins a6, a3, a2 , a1, and a0 must be as shown in ta b l e 5 . in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see ta b l e 2 ). ta b l e 5 shows the re- maining address bits that are don?t care. when all necessary bits have been set as required, the programming equipment may then read the corresponding iden- tifier code on dq7?dq0. to access the autoselect codes in-system, the host system can issue the autose- lect command via the command register, as shown in ta b l e 1 2 . this method does not require v id . refer to the autoselect command sequence section for more information. sa123 1 1 1 0 1 1 128/64 07b0000?07bffff sa124 1 1 1 1 0 0 128/64 07c0000?07cffff sa125 1 1 1 1 0 1 128/64 07d0000?07dffff sa126 1 1 1 1 1 0 128/64 07e0000?07effff sa127 1 1 1 1 1 1 128/64 07f0000?07fffff table 4. sector address table?s29gl128n (continued) sector a22?a16 sector size (kbytes/ kwords) address range (in hexadecimal)
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 53 advance information ta b l e 5 . autoselect codes, (high voltage method) legend: l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. sector protection the device features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: persistent sector protection a command sector protection method that replaces the old 12 v controlled pro- tection method. password sector protection a highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted wp# hardware protection a write protect pin that can prevent program or erase operations in the outermost sectors. the wp# hardware protection feature is always available, independent of the software managed protection method chosen. selecting a sector protection mode all parts default to operate in the persistent sector protection mode. the cus- tomer must then choose if the persistent or password protection method is most desirable. there are two one-time programmable non-volatile bits that define which sector protection method will be used. if the customer decides to continue description ce# oe# we # a22 to a15 a14 to a10 a9 a8 to a7 a6 a5 to a4 a3 to a2 a1 a0 dq8 to dq15 dq7 to dq0 manufacturer id : spansion product llhxxv id x l x l l l 00 01h device id s29gl512n cycle 1 llhxxv id xl x llh 22 7eh cycle 2 h h l 22 23h cycle 3 h h h 22 01h device id s29gl256n cycle 1 llhxxv id xl x llh 22 7eh cycle 2 h h l 22 22h cycle 3 h h h 22 01h device id s29gl128n cycle 1 llhxxv id xl x llh 22 7eh cycle 2 h h l 22 21h cycle 3 h h h 22 01h sector group protection verification llhsaxv id xl x l h l x 01h (protected), 00h (unprotected) secured silicon sector indicator bit (dq7), wp# protects highest address sector llhxxv id xl x l h h x 98h (factory locked), 18h (not factory locked) secured silicon sector indicator bit (dq7), wp# protects lowest address sector llhxxv id xl x l h h x 88h (factory locked), 08h (not factory locked)
54 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information using the persistent sector protection method, they must set the persistent sector protection mode locking bit . this will permanently set the part to op- erate only using persistent sector protection. if the customer decides to use the password method, they must set the password mode locking bit . this will permanently set the part to operate only using password sector protection. it is important to remember that setting either the persistent sector protec- tion mode locking bit or the password mode locking bit permanently selects the protection mode. it is not possible to switch between the two methods once a locking bit has been set. it is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. this is so that it is not possible for a system program or virus to later set the password mode locking bit, which would cause an unex- pected shift from the default persistent sector protection mode into the password protection mode. the device is shipped with all sectors unprotected. the factory offers the option of programming and protecting sectors at the factory prior to shipping the device through the expressflash? service. contact your sales representative for details. it is possible to determine whether a sector is protected or unprotected. see ?au- toselect command sequence? section on page 66 for details. advanced sector protection advanced sector protection features several levels of sector protection, which can disable both the program and erase operations in certain sectors. persistent sector protection is a method that replaces the old 12v controlled protection method. password sector protection is a highly sophisticated protection method that requires a password before changes to certain sectors are permitted. lock register the lock register consists of 3 bits (dq2, dq1, and dq0). these dq2, dq1, dq0 bits of the lock register are programmable by the user. users are not allowed to program both dq2 and dq1 bits of the lock register to the 00 state. if the user tries to program dq2 and dq1 bits of the lock register to the 00 state, the device will abort the lock register back to the default 11 state. the programming time of the lock register is same as the typical word programming time without uti- lizing the write buffer of the device. during a lock register programming sequence execution, the dq6 toggle bit i will toggle until the programming of the lock register has completed to indicate programming status. all lock register bits are readable to allow users to verify lock register statuses. the customer secured silicon sector protection bit is dq0, persistent protection mode lock bit is dq1, and password protection mode lock bit is dq2 are acces- sible by all users. each of these bits are non-volatile. dq15-dq3 are reserved and must be 1's when the user tries to program the dq2, dq1, and dq0 bits of the lock register. the user is not required to program dq2, dq1 and dq0 bits of the lock register at the same time. this allows users to lock the secured silicon sec- tor and then set the device either permanently into password protection mode or persistent protection mode and then lock the secured silicon sector at separate instances and time frames. ? secured silicon sector protection allows the user to lock the secured silicon sector area
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 55 advance information ? persistent protection mode lock bit allows the user to set the device perma- nently to operate in the persistent protection mode ? password protection mode lock bit allows the user to set the device perma- nently to operate in the password protection mode ta b l e 6 . lock register persistent sector protection the persistent sector protection method replaces the old 12 v controlled protec- tion method while at the same time enhancing flexibility by providing three different sector protection states: ? dynamically locked -the sector is protected and can be changed by a sim- ple command ? persistently locked -a sector is protected and cannot be changed ? unlocked -the sector is unprotected and can be changed by a simple com- mand in order to achieve these states, three types of ?bits? are going to be used: dynamic protection bit (dyb) a volatile protection bit is assigned for each sector. after power-up or hardware reset, the contents of all dyb bits are in the ?unprotected state?. each dyb is in- dividually modifiable through the dyb set command and dyb clear command. when the parts are first shipped, all of the persistent protect bits (ppb) are cleared into the unprotected state. the dyb bits and ppb lock bit are defaulted to power up in the cleared state or unprotected state - meaning the all ppb bits are changeable. the protection state for each sector is determined by the logical or of the ppb and the dyb related to that sector. for the sectors that have the ppb bits cleared, the dyb bits control whether or not the sector is protected or unprotected. by is- suing the dyb set and dyb clear command sequences, the dyb bits will be protected or unprotected, thus placing each sector in the protected or unpro- tected state. these are the so-called dynamic locked or unlocked states. they are called dynamic states because it is very easy to switch back and forth be- tween the protected and un-protected conditions. this allows software to easily protect sectors against inadvertent changes yet does not prevent the easy re- moval of protection when changes are needed. the dyb bits maybe set or cleared as often as needed. the ppb bits allow for a more static, and difficult to change, level of protection. the ppb bits retain their state across power cycles because they are non-volatile. individual ppb bits are set with a program command but must all be cleared as a group through an erase command. the ppb lock bit adds an additional level of protection. once all ppb bits are pro- grammed to the desired settings, the ppb lock bit may be set to the ?freeze state?. setting the ppb lock bit to the ?freeze state? disables all program and erase commands to the non-volatile ppb bits. in effect, the ppb lock bit locks the ppb bits into their current state. the only way to clear the ppb lock bit to the dq15-3 dq2 dq1 dq0 don?t care password protection mode lock bit persistent protection mode lock bit secured silicon sector protection bit
56 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information ?unfreeze state? is to go through a power cycle, or hardware reset. the software reset command will not clear the ppb lock bit to the ?unfreeze state?. system boot code can determine if any changes to the ppb bits are needed e.g. to allow new system code to be downloaded. if no changes are needed then the boot code can set the ppb lock bit to disable any further changes to the ppb bits during system operation. the wp# write protect pin adds a final level of hardware protection. when this pin is low it is not possible to change the contents of the wp# protected sectors. these sectors generally hold system boot code. so, the wp# pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. it is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. the sectors in the dynamic state are all unprotected. if there is a need to protect some of them, a simple dyb set command sequence is all that is necessary. the dyb set and dyb clear commands for the dynamic sectors switch the dyb bits to signify protected and unprotected, respectively. if there is a need to change the status of the persistently locked sectors, a few more steps are required. first, the ppb lock bit must be disabled to the ?unfreeze state? by either putting the device through a power-cycle, or hardware reset. the ppb bits can then be changed to reflect the desired settings. setting the ppb lock bit once again to the ?freeze state? will lock the ppb bits, and the device operates normally again. note: to achieve the best protection, it's recommended to execute the ppb lock bit set command early in the boot code, and protect the boot code by holding wp# = v il . persistent protection bit (ppb) a single persistent (non-volatile) protection bit is assigned to each sector. if a ppb is programmed to the protected state through the ?ppb program? command, that sector will be protected from program or erase operations will be read-only. if a ppb requires erasure, all of the sector ppb bits must first be erased in parallel through the ?all ppb erase? command. the ?all ppb erase? command will prepro- grammed all ppb bits prior to ppb erasing. all ppb bits erase in parallel, unlike programming where individual ppb bits are programmable. the ppb bits have the same endurance as the flash memory. programming the ppb bit requires the typical word programming time without uti- lizing the write buffer. during a ppb bit programming and a11 ppb bit erasing sequence execution, the dq6 toggle bit i will toggle until the programming of the ppb bit or erasing of all ppb bits has completed to indicate programming and erasing status. erasing all of the ppb bits at once requires typical sector erase time. during the erasing of all ppb bits, the dq3 sector erase timer bit will output a 1 to indicate the erasure of all ppb bits are in progress. when the erasure of all ppb bits has completed, the dq3 sector erase timer bit will output a 0 to indicate that all ppb bits have been erased. reading the ppb status bit requires the initial access time of the device. persistent protection bit lock (ppb lock bit) a global volatile bit. when set to the ?freeze state?, the ppb bits cannot be changed. when cleared to the ?unfreeze state?, the ppb bits are changeable. there is only one ppb lock bit per device. the ppb lock bit is cleared to the ?un-
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 57 advance information freeze state? after power-up or hardware reset. there is no command sequence to unlock or ?unfreeze? the ppb lock bit. configuring the ppb lock bit to the freeze state requires approximately 100ns. reading the ppb lock status bit requires the initial access time of the device. ta b l e 7 . sector protection schemes ta b l e 7 contains all possible combinations of the dyb bit, ppb bit, and ppb lock bit relating to the status of the sector. in summary, if the ppb bit is set, and the ppb lock bit is set, the sector is protected and the protection cannot be removed until the next power cycle or hardware reset clears the ppb lock bit to ?unfreeze state?. if the ppb bit is cleared, the sector can be dynamically locked or unlocked. the dyb bit then controls whether or not the sector is protected or unprotected. if the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. a program command to a protected sec- tor enables status polling for approximately 1 s before the device returns to read mode without having modified the contents of the protected sector. an erase command to a protected sector enables status polling for approximately 50 s after which the device returns to read mode without having erased the protected sector. the programming of the dyb bit, ppb bit, and ppb lock bit for a given sec- tor can be verified by writing a dyb status read, ppb status read, and ppb lock status read commands to the device. the autoselect sector protection verification outputs the or function of the dyb bit and ppb bit per sector basis. when the or function of the dyb bit and ppb bit is a 1, the sector is either protected by dyb or ppb or both. when the or function of the dyb bit and ppb bit is a 0, the sector is unprotected through both the dyb and ppb. persistent protection mode lock bit like the password protection mode lock bit, a persistent protection mode lock bit exists to guarantee that the device remain in software sector protection. once programmed, the persistent protection mode lock bit prevents programming of the password protection mode lock bit. this guarantees that a hacker could not place the device in password protection mode. the password protection mode lock bit resides in the ?lock register?. protection states sector state dyb bit ppb bit ppb lock bit unprotect unprotect unfreeze unprotected ? ppb and dyb are changeable unprotect unprotect freeze unprotected ? ppb not changeable, dyb is changeable unprotect protect unfreeze protected ? ppb and dyb are changeable unprotect protect freeze protected ? ppb not changeable, dyb is changeable protect unprotect unfreeze protected ? ppb and dyb are changeable protect unprotect freeze protected ? ppb not changeable, dyb is changeable protect protect unfreeze protected ? ppb and dyb are changeable protect protect freeze protected ? ppb not changeable, dyb is changeable
58 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information password sector protection the password sector protection method allows an even higher level of security than the persistent sector protection method. there are two main differences be- tween the persistent sector protection and the password sector protection methods: ? when the device is first powered on, or comes out of a reset cycle, the ppb lock bit is set to the locked state, or the freeze state, rather than cleared to the unlocked state, or the unfreeze state. ? the only means to clear and unfreeze the ppb lock bit is by writing a unique 64-bit password to the device. the password sector protection method is otherwise identical to the persistent sector protection method. a 64-bit password is the only additional tool utilized in this method. the password is stored in a one-time programmable (otp) region outside of the flash memory. once the password protection mode lock bit is set, the password is permanently set with no means to read, program, or erase it. the password is used to clear and unfreeze the ppb lock bit. the password unlock command must be written to the flash, along with a password. the flash device internally com- pares the given password with the pre-programmed password. if they match, the ppb lock bit is cleared to the ?unfreezed state?, and the ppb bits can be altered. if they do not match, the flash device does nothing. there is a built-in 2 s delay for each ?password check? after the valid 64-bit password has been entered for the ppb lock bit to be cleared to the ?unfreezed state?. this delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. password and password protection mode lock bit in order to select the password sector protection method, the customer must first program the password. the factory recommends that the password be somehow correlated to the unique electronic serial number (esn) of the particular flash de- vice. each esn is different for every flash device; therefore each password should be different for every flash device. while programming in the password region, the customer may perform password read operations. once the desired pass- word is programmed in, the customer must then set the password protection mode lock bit. this operation achieves two objectives: 1. it permanently sets the device to operate using the password protection mode. it is not possible to reverse this function. 2. it also disables all further commands to the password region. all program, and read operations are ignored. both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. the user must be sure that the password sector protec- tion method is desired when programming the password protection mode lock bit. more importantly, the user must be sure that the password is correct when the password protection mode lock bit is programmed. due to the fact that read operations are disabled, there is no means to read what the password is after- wards. if the password is lost after programming the password protection mode lock bit, there will be no way to clear and unfreeze the ppb lock bit. the pass- word protection mode lock bit, once programmed, prevents reading the 64-bit password on the dq bus and further password programming. the password pro- tection mode lock bit is not erasable. once password protection mode lock bit is
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 59 advance information programmed, the persistent protection mode lock bit is disabled from program- ming, guaranteeing that no changes to the protection scheme are allowed. 64-bit password the 64-bit password is located in its own memory space and is accessible through the use of the password program and password read commands. the password function works in conjunction with the password protection mode lock bit, which when programmed, prevents the password read command from reading the con- tents of the password on the pins of the device. persistent protection bit lock (ppb lock bit) a global volatile bit. the ppb lock bit is a volatile bit that reflects the state of the password protection mode lock bit after power-up reset. if the password protec- tion mode lock bit is also programmed after programming the password, the password unlock command must be issued to clear and unfreeze the ppb lock bit after a hardware reset (reset# asserted) or a power-up reset. successful exe- cution of the password unlock command clears and unfreezes the ppb lock bit, allowing for sector ppb bits to be modified. without issuing the password unlock command, while asserting reset#, taking the device through a power-on reset, or issuing the ppb lock bit set command sets the ppb lock bit to a the ?freeze state?. if the password protection mode lock bit is not programmed, the device defaults to persistent protection mode. in the persistent protection mode, the ppb lock bit is cleared to the ?unfreeze state? after power-up or hardware reset. the ppb lock bit is set to the ?freeze state? by issuing the ppb lock bit set command. once set to the ?freeze state? the only means for clearing the ppb lock bit to the ?unfreeze state? is by issuing a hardware or power-up reset. the password unlock com- mand is ignored in persistent protection mode. reading the ppb lock bit requires a 200ns access time. secured silicon sector flash memory region the secured silicon sector feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn). the secured silicon sector is 256 bytes in length, and uses a secured silicon sector indicator bit (dq7) to indicate whether or not the secured silicon sector is locked when shipped from the factory. this bit is permanently set at the factory and can- not be changed, which prevents cloning of a factory locked part. this ensures the security of the esn once the product is shipped to the field. the factory offers the device with the secured silicon sector either customer lockable (standard shipping option) or factory locked (contact an amd sales rep- resentative for ordering information). the customer-lockable version is shipped with the secured silicon sector unprotected, allowing customers to program the sector after receiving the device. the customer-lockable version also has the se- cured silicon sector indicator bit permanently set to a ?0.? the factory-locked version is always protected when shipped from the factory, and has the secured silicon sector indicator bit permanently set to a ?1.? thus, the secured silicon sector indicator bit prevents customer-lockable devices from being used to re- place devices that are factory locked. note that the acc function and unlock bypass modes are not available when the secured silicon sector is enabled.
60 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information the secured silicon sector address space in this device is allocated as follows: the system accesses the secured silicon sector through a command sequence (see ?write protect (wp#)?). after the system has written the enter secured sil- icon sector command sequence, it may read the secured silicon sector by using the addresses normally occupied by the first sector (sa0). this mode of operation continues until the system issues the exit secured silicon sector command se- quence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to sector sa0. customer lockable: secured silicon sector not programmed or protected at the factory unless otherwise specified, the device is shipped such that the customer may program and protect the 256-byte secured silicon sector. the system may program the secured silicon sector using the write-buffer, ac- celerated and/or unlock bypass methods, in addition to the standard programming command sequence. see ?command definitions? . programming and protecting the secured silicon sector must be used with cau- tion since, once protected, there is no procedure available for unprotecting the secured silicon sector area and none of the bits in the secured silicon sector memory space can be modified in any way. the secured silicon sector area can be protected using one of the following procedures: ? write the three-cycle enter secured silicon sector region command se- quence, and then follow the in-system sector protect algorithm, except that reset# may be at either v ih or v id . this allows in-syste m protection of the secured silicon sector without raising any device pin to a high voltage. note that this method is only applicable to the secured silicon sector. ? to verify the protect/unprotect status of the secured silicon sector, follow the algorithm. once the secured silicon sector is programmed, locked and verified, the system must write the exit secured silicon sector region command sequence to return to reading and writing within the remainder of the array. factory locked: secured silicon sector programmed and protected at the factory in devices with an esn, the secured sili con sector is protected when the device is shipped from the factory. the secured silicon sector cannot be modified in any way. an esn factory locked device has an 16-byte random esn at addresses 000000h?000007h. please contact your sales representative for details on order- ing esn factory locked devices. customers may opt to have their code programmed by the factory through the expressflash service (express flash factory locked). the devices are then shipped from the factory with the secured silicon sector permanently locked. contact your sales representative for details on using the expressflash service. secured silicon sector address range customer lockable esn factory locked expressflash factory locked 000000h?000007h determined by customer esn esn or determined by customer 000008h?00007fh unavailable determined by customer
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 61 advance information write protect (wp#) the write protect function provides a hardware method of protecting the first or last sector group without using v id . write protect is one of two functions provided by the wp#/acc input. if the system asserts v il on the wp#/acc pin, the device disables program and erase functions in the first or last sector group independently of whether those sector groups were protected or unprotected using the method described in ?ad- vanced sector protection? section on page 54 . note that if wp#/acc is at v il when the device is in the standby mode, the maximum input load current is in- creased. see the table in ?dc characteristics? section on page 90 . if the system asserts v ih on the wp#/acc pin, the device reverts to whether the first or last sector was previously set to be protected or un- protected using the method described in ?sector group protection and unprotection?. note that wp# has an internal pullup; when uncon- nected, wp# is at v ih . hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to ta b l e 1 2 for com- mand definitions). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this pro- tects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up. common flash memory interface (cfi) the common flash interface (cfi) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified soft- ware algorithms to be used for entire families of devices. software support can
62 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information then be device-independent, jedec id-independent, and forward- and back- ward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h, any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 8-11. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the au- toselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 8?11. the system must write the reset command to return the device to reading array data. for further information, please refer to the cfi specification and cfi publication 100, available via the world wide web at http://www.amd.com/flash/cfi. alter- natively, contact your sales representative for copies of these documents. table 8. cfi query identification string addresses (x16) data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists)
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 63 advance information table 9. system interface string addresses (x16) data description 1bh 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0007h typical timeout per single byte/word write 2 n s 20h 0007h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 000ah typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0001h max. timeout for byte/word write 2 n times typical 24h 0005h max. timeout for buffer write 2 n times typical 25h 0004h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
64 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information table 10. device geometry definition addresses (x16) data description 27h 001ah 0019h 0018h device size = 2 n byte 1a = 512 mb, 19 = 256 mb, 18 = 128 mb 28h 29h 0002h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 0005h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 0001h number of erase block regions within device (01h = uniform device, 02h = boot device) 2dh 2eh 2fh 30h 00xxh 000xh 0000h 000xh erase block region 1 information (refer to the cfi specification or cfi publication 100) 00ffh, 001h, 0000h, 0002h = 512 mb 00ffh, 0000h, 0000h, 0002h = 256 mb 007fh, 0000h, 0000h, 0002h = 128 mb 31h 32h 33h 34h 0000h 0000h 0000h 0000h erase block region 2 information (refer to cfi publication 100) 35h 36h 37h 38h 0000h 0000h 0000h 0000h erase block region 3 information (refer to cfi publication 100) 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information (refer to cfi publication 100)
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 65 advance information table 11. primary vendor-specific extended query command definitions writing specific address and data commands or sequences into the command register initiates device operations. ta b l e 1 2 defines the valid register command sequences. writing incorrect address and data values or writing them in the im- proper sequence may place the device in an unknown state. a reset command is then required to return the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the ac characteristics section for timing diagrams. addresses (x16) data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii 44h 0033h minor version number, ascii 45h 0010h address sensitive unlock (bits 1-0) 0 = required, 1 = not required process technology (bits 7-2) 0100b = 110 nm mirrorbit 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 0000h sector temporary unprotect 00 = not supported, 01 = supported 49h 0008h sector protect/unprotect scheme 0008h = advanced sector protection 4ah 0000h simultaneous operation 00 = not supported, x = number of sectors in bank 4bh 0000h burst mode type 00 = not supported, 01 = supported 4ch 0002h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 00b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 00c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 00xxh wp# protection 04h = uniform sectors bottom wp# protect, 05h = uniform sectors top wp# protect 50h 0001h program suspend 00h = not supported, 01h = supported
66 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non- erase-suspended sector. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same ex- ception. see the erase suspend/erase resume commands section for more information. the system must issue the reset command to return the device to the read (or erase-suspend-read) mode if dq5 goes hi gh during an active program or erase operation, or if the device is in the autoselect mode. see the next section, reset command, for more information. see also requirements for reading array data in the device bus operations sec- tion for more information. the read-only operations??ac characteristics? section provides the read parameters, and figure 11 shows the timing diagram. reset command writing the reset command resets the device to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to the read mode. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to the read mode. if the program command sequence is written while the device is in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. once programming begins, however, the device ig- nores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if the device entered the autoselect mode while in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in erase suspend). note that if dq1 goes high during a write buffer programming operation, the sys- tem must write the write-to-buffer-abort reset command sequence to reset the device for the next operation. autoselect command sequence the autoselect command sequence allows the host system to access the manu- facturer and device codes, and determine whether or not a sector is protected. ta b l e 1 2 shows the address and data requiremen ts. this method is an alternative to that shown in ta b l e 5 , which is intended for prom programmers and requires v id on address pin a9. the autoselect command sequence may be written to an
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 67 advance information address that is either in the read or erase-suspend-read mode. the autoselect command may not be written while the device is actively programming or erasing. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the autoselect command. the device then enters the autoselect mode. the system may read at any address any number of times without initiating another autoselect command sequence: ? a read cycle at address xx00h returns the manufacturer code. ? three read cycles at addresses 01h, 0eh, and 0fh return the device code. ? a read cycle to an address containing a sector address (sa), and the address 02h on a7?a0 in word mode returns 01h if the sector is protected, or 00h if it is unprotected. the system must write the reset command to return to the read mode (or erase- suspend-read mode if the device was previously in erase suspend). enter secured silicon sector/exit secured silicon sector command sequence the secured silicon sector region provides a secured data area containing an 8- word/16-byte random electronic serial number (esn). the system can access the secured silicon sector region by issuing the three-cycle enter secured silicon sector command sequence. the device continues to access the secured silicon sector region until the system issues the four-cycle exit secured silicon sector command sequence. the exit secured silicon sector command sequence returns the device to normal operation. ta b l e 1 2 shows the address and data require- ments for both command sequences. see also ?secured silicon sector flash memory region? for further information. note that the acc function and unlock bypass modes are not available when the secured silicon sector is enabled. word program command sequence programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up com- mand. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further con- trols or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. ta b l e 1 2 shows the address and data requirements for the word program command sequence. when the embedded program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. the system can determine the status of the program operation by using dq7 or dq6. refer to the write op- eration status section for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that the secured silicon sector, autoselect, and cfi functions are unavailable when a program operation is in progress. note that a hardware reset immediately terminates the program operation. the pro- gram command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. programming is allowed in any sequence of address locations and across sector boundaries. programming to the same word address multiple times without in- tervening erases (incremental bit programming) requires a modified programming method. for such application requirements, please contact your
68 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information local spansion representative. word programming is supported for backward compatibility with existing flash driver software and for occasional writing of in- dividual words. use of write buffer programming is strongly recommended for general programming use when more than a few words are to be programmed. the effective word programming time using write buffer programming is much shorter than the single word programming time. any word cannot be pro- grammed from ?0? back to a ?1.? attempting to do so may cause the device to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was successful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass program com- mand sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. ta b l e 1 2 shows the requirements for the command sequence. during the unlock bypass mode, only the unlock bypass program and unlock by- pass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. (see ta b l e 12 ). write buffer programming write buffer programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. this results in faster effective programming time than the standard programming algorithms. the write buffer programming command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer load command written at the sector address in which programming will occur. the fourth cycle writes the sec- tor address and the number of word locations, minus one, to be programmed. for example, if the system will program 6 unique address locations, then 05h should be written to the device. this tells the device how many write buffer addresses will be loaded with data and therefore when to expect the program buffer to flash command. the number of locations to program cannot exceed the size of the write buffer or the operation will abort. the fifth cycle writes the first address location and data to be programmed. the write-buffer-page is selected by address bits a max ?a 4 . all subsequent address/ data pairs must fall within the selected-write-buffer-page. the system then writes the remaining address/data pairs into the write buffer. write buffer loca- tions may be loaded in any order. the write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (this means write buffer programming cannot be performed across multiple write-buffer pages. this also means that write buffer program- ming cannot be performed across multiple sectors. if the system attempts to load programming data outside of the selected write-buffer page, the operation will abort.)
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 69 advance information note that if a write buffer address location is loaded multiple times, the address/ data pair counter will be decremented for every data load operation. the host system must therefore account for loadin g a write-buffer location more than once. the counter decrements for each data load operation, not for each unique write-buffer-address location. note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. once the specified number of write buffer locations have been loaded, the system must then write the program buffer to flash command at the sector address. any other address and data combination aborts the write buffer programming oper- ation. the device then begins programming. data polling should be used while monitoring the last address location loaded into the write buffer. dq7, dq6, dq5, and dq1 should be monitored to determine the device status during write buffer programming. the write-buffer programming operation can be suspended using the standard program suspend/resume commands. upon successful completion of the write buffer programming operation, the device is ready to execute the next command. the write buffer programming sequence can be aborted in the following ways: ? load a value that is greater than the page buffer size during the number of locations to program step. ? write to an address in a sector different than the one specified during the write-buffer-load command. ? write an address/data pair to a different write-buffer-page than the one se- lected by the starting address during the write buffer data loading stage of the operation. ? write data other than the confirm command after the specified number of data load cycles. the abort condition is indicated by dq1 = 1, dq7 = data# (for the last address location loaded), dq6 = toggle, and dq5=0. a write-to-buffer-abort reset com- mand sequence must be written to reset the device for the next operation. note that the full 3-cycle write-to-buffer-abort reset command sequence is required when using write-buffer-programming features in unlock bypass mode. write buffer programming is allowed in any sequence. note that the secured sil- icon sector, autoselect, and cfi functions are unavailable when a program operation is in progress. this flash device is capable of handling multiple write buffer programming operations on the same write buffer address range without intervening erases. for applications requiring incremental bit programming, a modified programming method is required, please contact your local spansion representative. any bit in a write buffer address range cannot be pro- grammed from ?0? back to a ?1.? attempting to do so may cause the device to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was successful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? accelerated program the device offers accelerated program operations through the wp#/acc pin. when the system asserts v hh on the wp#/acc pin, the device automatically en- ters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the wp#/acc pin to accelerate the operation. note that the wp#/ acc pin must not
70 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information be at v hh for operations other than accelerated programming, or device damage may result. wp# has an internal pullup; when unconnected, wp# is at v ih . figure 2 illustrates the algorithm for the program operation. refer to the erase and program operations??ac characteristics? section for parameters, and figure 14 for timing diagrams. figure 1. write buffer programming operation write ?write to buffer? command and sector address write number of addresses to program minus 1(wc) and sector address write program buffer to flash sector address write first address/data write to a different sector address fail or abort pa s s read dq15 - dq0 at last loaded address read dq15 - dq0 with address = last loaded address write next address/data pair wc = wc - 1 wc = 0 ? part of ?write to buffer? command sequence ye s ye s ye s ye s ye s ye s no no no no no no abort write to buffer operation? dq7 = data? dq7 = data? dq5 = 1? dq1 = 1? write to buffer aborted. must write ?write-to-buffer abort reset? command sequence to return to read mode. (note 1) (note 2) (note 3) notes: 1. when sector address is specified, any address in the selected sector is acceptable. however, when loading write-buffer address locations with data, all addresses must fall within the selected write-buffer page. 2. dq7 may change simultaneously with dq5. therefore, dq7 should be verified. 3. if this flowchart location was reached because dq5= ?1?, then the device failed. if this flowchart location was reached because dq1= ?1?, then the write to buffer operation was aborted. in either case, the proper reset command must be written before the device can begin another operation. if dq1=1, write the write- buffer-programming-abort-reset command. if dq5=1, write the reset command. 4. see table 12 for command sequences required for write buffer programming.
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 71 advance information figure 2. program operation program suspend/program resume command sequence the program suspend command allows the system to interrupt a programming operation or a write to buffer programming operation so that data can be read from any non-suspended sector. when th e program suspend command is written during a programming process, the device halts the program operation within 15 s maximum (5 s typical) and updates the status bits. addresses are not re- quired when writing the program suspend command. after the programming operation has been suspended, the system can read array data from any non-suspended sector. the program suspend command may also be issued during a programming operation while an erase is suspended. in this case, data may be read from any addresses not in erase suspend or program suspend. if a read is needed from the secured silicon sector area (one-time pro- gram area), then user must use the prop er command sequences to enter and exit this region. note that the secured silicon sector autoselect, and cfi functions are unavailable when program operation is in progress. the system may also write the autoselect command sequence when the device is in the program suspend mode. the system can read as many autoselect codes as required. when the device exits the autoselect mode, the device reverts to the program suspend mode, and is ready for another valid operation. see autoselect command sequence for more information. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress note: see table 12 for program command sequence.
72 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information after the program resume command is written, the device reverts to program- ming. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see write op- eration status for more information. the system must write the program resume command (address bits are don?t care) to exit the program suspend mode and continue the programming opera- tion. further writes of the resume command are ignored. another program suspend command can be written after the device has resume programming. figure 3. program suspend/program resume chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is ini- tiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto- matically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. ta b l e 1 2 shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, or dq2. refer to the write operation status section for information on these status bits. program operation or write-to-buffer sequence in progress write program suspend command sequence command is also valid for erase-suspended-program operations autoselect and secsi sector read operations are also allowed data cannot be read from erase- o r program-suspended sectors write program resume command sequence read data as required done reading? no yes write address/data xxxh/30h device reverts to operation prior to program suspend write address/data xxxh/b0h wait 15 s
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 73 advance information any commands written during the chip er ase operation are ignored, including erase suspend commands. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to en- sure data integrity. figure 4 illustrates the algorithm for the erase operation. note that the secured silicon sector, autoselect, and cfi functions are unavailable when an erase operation in is progress. refer to the ?erase and programming perfor- mance? section on page 102 in the ac characteristics section for parameters, and figure 16 section for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two addi- tional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. ta b l e 1 2 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the em- bedded erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector erase address and command following the exceeded time- out may or may not be accepted. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any com- mand other than sector erase or erase suspend during the time-out period resets the device to the read mode. note that the secured silicon sector, autoselect, and cfi functions are unavailable when an erase op- eration in is progress. the system must rewrite the command sequence and any additional addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out (see the section on dq3: sector erase timer.). the time-out begins from the ris- ing edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by reading dq7, dq6, or dq2 in the erasing sector. refer to the write operation status section for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset im- mediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. figure 4 illustrates the algorithm for the erase operation. refer to the erase and program operations table in the ac characteristics section for parameters, and figure 16 section for timing diagrams.
74 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information figure 4. erase operation erase suspend/erase resume commands the erase suspend command, b0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, includ- ing the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a typical of 5 s ( maximum of 20 s) to suspend the erase operation. however, when the erase suspend command is written during the sec- tor erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the device enters the erase-sus- pend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) reading at any address within erase-suspended sectors produces sta- tus information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write operation status section for information on these status bits. after an erase-suspended program operation is complete, the device returns to the erase-suspend-read mode. the system can determine the status of the pro- start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress notes: 1. see table 12 for program command sequence. 2. see the section on dq3 for information on the sector erase timer.
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 75 advance information gram operation using the dq7 or dq6 status bits, just as in the standard word program operation. refer to the write operation status section for more information. in the erase-suspend-read mode, the system can also issue the autoselect com- mand sequence. refer to the ?autoselect mode? section and ?autoselect command sequence? section on page 66 sections for details. to resume the sector erase operation, the system must write the erase resume command. the address of the erase-suspended sector is required when writing this command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing. it is important to allow an interval of at least 5 ms between erase resume and erase suspend. lock register command set definitions the lock register command set permits the user to one-time program the se- cured silicon sector protection bit, persistent protection mode lock bit, and password protection mode lock bit. the lock register bits are all readable after an initial access delay. the lock register command set entry command sequence must be issued prior to any of the following commands listed, to enable proper command execution. note that issuing the lock register command set entry command disables reads and writes for the flash memory . ? lock register program command ? lock register read command the lock register command set exit command must be issued after the ex- ecution of the commands to reset the device to read mode. otherwise the device will hang. if this happens, the flash device must be reset. please refer to reset# for more information. it is important to note that the device will be in either per- sistent protection mode or password pr otection mode depending on the mode selected prior to the device hang. for either the secured silicon sector to be locked, or the device to be perma- nently set to the persistent protection mode or the password protection mode, the associated lock register bits must be programmed. note that the persistent protection mode lock bit and password protection mode lock bit can never be programmed together at the same time. if so, the lock register program operation will abort . the lock register command set exit command must be initiated to re- enable reads and writes to the main memory. password protection command set definitions the password protection command set permits the user to program the 64-bit password, verify the programming of the 64-bit password, and then later unlock the device by issuing the valid 64-bit password. the password protection command set entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. note that issuing the password protection command set entry command disabled reads and writes the main memory.
76 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information ? password program command ? password read command ? password unlock command the password program command permits programming the password that is used as part of the hardware protection scheme. the actual password is 64-bits long. there is no special addressing order required for programming the pass- word. the password is programmed in 8-bit or 16-bit portions. each portion requires a password program command. once the password is written and verified, the password protection mode lock bit in the ?lock register? must be programmed in order to prevent verification. the password program command is only capable of programming ?0?s. programming a ?1? after a cell is programmed as a ?0? results in a time-out by the embedded program algorithm tm with the cell remaining as a ?0?. the password is all f?s when shipped from the factory. all 64-bit password combinations are valid as a password. the password read command is used to verify the password. the password is verifiable only when the password protection mode lock bit in the ?lock register? is not programmed. if the password protection mode lock bit in the ?lock regis- ter? is programmed and the user attempts to read the password, the device will always drive all f?s onto the dq databus. the lower two address bits (a1?a0) for word mode and (a1?a-1) for by byte mode are valid during the password read, password program, and password un- lock commands. writing a ?1? to any other address bits (a max -a2) will abort the password read and password program commands. the password unlock command is used to clear the ppb lock bit to the ?unfreeze state? so that the ppb bits can be modified. the exact password must be entered in order for the unlocking function to occur. this 64-bit password unlock com- mand sequence will take at least 2 s to process each time to prevent a hacker from running through the all 64-bit combinations in an attempt to correctly match the password. if another password unlock is issued before the 64-bit password check execution window is completed, the command will be ignored. if the wrong address or data is given during password unlock command cycle, the device may enter the write-to- buffer abort state. in order to exit the write-to-abort state, the write-to- buffer-abort-reset command must be given. otherwise the device will hang. the password unlock function is accomplished by writing password unlock com- mand and data to the device to perform the clearing of the ppb lock bit to the ?unfreeze state?. the password is 64 bits long. a1 and a0 are used for matching. writing the password unlock command does not need to be address order spe- cific. an example sequence is starting with the lower address a1-a0=00, followed by a1-a0=01, a1-a0=10, and a1-a0=11 if the device is configured to operate in word mode. approximately 2 s is required for unlocking the device after the valid 64-bit password is given to the device. it is the responsibility of the mi- croprocessor to keep track of the entering the portions of the 64-bit password with the password unlock command, the order, and when to read the ppb lock bit to confirm successful password unlock. in order to re-lock the device into the password protection mode, the ppb lock bit set com- mand can be re-issued.
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 77 advance information the password protection command set exit command must be issued after the execution of the commands listed previously to reset the device to read mode. otherwise the device will hang. note that issuing the password protection command set exit command re- enables reads and writes for the main memory. non-volatile sector protection command set definitions the non-volatile sector protection command set permits the user to program the persistent protection bits (ppb bits), erase all of the persistent protection bits (ppb bits), and read the logic state of the persistent protection bits (ppb bits). the non-volatile sector protection command set entry command se- quence must be issued prior to any of the commands listed following to enable proper command execution. note that issuing the non-volatile sector protection command set entry command disables reads and writes for the main memory . ? ppb program command the ppb program command is used to program, or set, a given ppb bit. each ppb bit is individually programmed (but is bulk erased with the other ppb bits). the specific sector address (a24-a16 for s29gl512n, a23-a16 for s29gl256n, a22- a16 for s29gl128n) is written at the same time as the program command. if the ppb lock bit is set to the ?freeze state?, the ppb program command will not exe- cute and the command will time-out without programming the ppb bit. ? all ppb erase command the all ppb erase command is used to erase all ppb bits in bulk. there is no means for individually erasing a specific ppb bit. unlike the ppb program, no spe- cific sector address is required. however, when the all ppb erase command is issued, all sector ppb bits are erased in parallel. if the ppb lock bit is set to ?freeze state?, the all ppb erase command will not execute and the command will time-out without erasing the ppb bits. the device will preprogram all ppb bits prior to erasing when issuing the all ppb erase command. also note that the total number of ppb program/erase cycles has the same endurance as the flash memory array. ? ppb status read command the programming state of the ppb for a given sector can be verified by writing a ppb status read command to the device. this requires an initial access time latency. the non-volatile sector protection command set exit command must be issued after the execution of the commands listed previously to reset the device to read mode. note that issuing the non-volatile sector protection command set exit command re-enables reads and writes for the main memory . global volatile sector protection freeze command set the global volatile sector protection freeze command set permits the user to set the ppb lock bit and reading the logic state of the ppb lock bit. the global volatile sector protection freeze command set entry com- mand sequence must be issued prior to any of the commands listed following to enable proper command execution.
78 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information reads and writes from the main memory are not allowed. ? ppb lock bit set command the ppb lock bit set command is used to set the ppb lock bit to the ?freeze state? if it is cleared either at reset or if the password unlock command was successfully executed. there is no ppb lock bit clear command. once the ppb lock bit is set to the ?freeze state?, it cannot be cleared unless the device is taken through a power-on clear (for persistent protection mode) or the password unlock command is executed (for password protection mode). if the password protection mode lock bit is programmed, the ppb lock bit status is reflected as set to the ?freeze state?, even after a power-on reset cycle. ? ppb lock bit status read command the programming state of the ppb lock bit can be verified by executing a ppb lock bit status read command to the device. the global volatile sector protection freeze command set exit command must be issued after the execution of the commands listed previously to reset the device to read mode. volatile sector protection command set the volatile sector protection command set permits the user to set the dynamic protection bit (dyb) to the ?protected state?, clear the dynamic protection bit (dyb) to the ?unprotected state?, and read the logic state of the dynamic protec- tion bit (dyb). the volatile sector protection command set entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. note that issuing the volatile sector protection command set entry com- mand disables reads and writes from main memory . ? dyb set command ? dyb clear command the dyb set and dyb clear commands are used to protect or unprotect a dyb for a given sector. the high order address bits are issued at the same time as the code 00h or 01h on dq7-dq0. all other dq data bus pins are ignored during the data write cycle. the dyb bits are modifiable at any time, regardless of the state of the ppb bit or ppb lock bit. the dyb bits are cleared to the ?unprotected state? at power-up or hardware reset. ?dyb status read command the programming state of the dyb bit for a given sector can be verified by writing a dyb status read command to the device. this requires an initial access delay. the volatile sector protection command set exit command must be issued after the execution of the commands listed previously to reset the device to read mode. note that issuing the volatile sector protection command set exit com- mand re-enables reads and writes to the main memory .
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 79 advance information secured silicon sector entry command the secured silicon sector entry command allows the following commands to be executed ? read from secured silicon sector ? program to secured silicon sector once the secured silicon sector entry command is issued, the secured silicon sector exit command has to be issued to exit secured silicon sector mode. secured silicon sector exit command the secured silicon sector exit command may be issued to exit the secured sil- icon sector mode.
80 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information command definitions ta b l e 1 2 . s29gl512n, s29gl256n, s29gl1 28n command definitions, x16 command (notes) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (6) 1 ra rd reset (7) 1 xxx f0 autoselect (note 8) manufacturer id 4 555 aa 2aa 55 555 90 x00 01 device id 4 555 aa 2aa 55 555 90 x01 227e x0e note 17 x0f note 17 sector protect verify 4 555 aa 2aa 55 555 90 (sa) x02 xx00 xx01 secure device verify (9) 4 555 aa 2aa 55 555 90 x03 note 10 cfi query (11) 1 55 98 program 4 555 aa 2aa 55 555 a0 pa pd write to buffer 3 555 aa 2aa 55 sa 25 sa wc pa pd wbl pd program buffer to flash (confirm) 1 sa 29 write-to-buffer-abort reset (16) 3 555 aa 2aa 55 555 f0 unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program (12) 2 xxx a0 pa pd unlock bypass sector erase (12) 2 xxx 80 sa 30 unlock bypass chip erase (12) 2 xxx 80 xxx 10 unlock bypass reset (13) 2 xxx 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend/program suspend (14) 1 xxx b0 erase resume/program resume (15) 1 xxx 30 sector command definitions secured silicon sector secured silicon sector entry 3 555 aa 2aa 55 555 88 secured silicon sector exit (18) 4 555 aa 2aa 55 555 90 xx 00 lock register command set definitions lock register lock register command set entry 3 555 aa 2aa 55 555 40 lock register bits program (22) 2 xxx a0 xxx data lock register bits read (22) 1 00 data lock register command set exit (18, 23) 2 xxx 90 xxx 00 password protection command set definitions
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 81 advance information legend: x = don?t care ra = address of the memory to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of the we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a max ?a16 uniquely select any sector. wbl = write buffer location. the address must be within the same write buffer page as pa. password password protection command set entry 3 555 aa 2aa 55 555 60 password program (20) 2 xxx a0 pwa x pwd x password read (19) 4 xxx pwd 0 01 pwd 1 02 pwd 2 03 pwd 3 password unlock (19) 7 00 25 00 03 00 pwd 0 01 pwd 1 02 pwd 2 03 pwd 3 00 29 password protection command set exit (18, 23) 2 xxx 90 xxx 00 non-volatile sector protection command set definitions ppb nonvolatile sector protection command set entry 3 555 aa 2aa 55 555 c0 ppb program (24, 25) 2 xxx a0 sa 00 all ppb erase 2 xxx 80 00 30 ppb status read (25) 1 sa rd (0) non-volatile sector protection command set exit (18) 2 xxx 90 xxx 00 global non-volatile sector protection freeze command set definitions ppb lock bit global non-volatile sector protection freeze command set entry 3 555 aa 2aa 55 555 50 ppb lock bit set (25) 2 xxx a0 xxx 00 ppb lock status read (25) 1 xxx rd (0) global non-volatile sector protection freeze command set exit (18) 2 xxx 90 xxx 00 volatile sector protection command set definitions dyb volatile sector protection command set entry 3 555 aa 2aa 55 555 e0 dyb set (24, 25) 2 xxx a0 sa 00 dyb clear (25) 2 xxx a0 sa 01 dyb status read (25) 1 sa rd (0) volatile sector protection command set exit (18) 2 xxx 90 xxx 00 command (notes) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data
82 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information wc = word count is the number of write buffer locations to load minus 1. pwd = password pwd x = password word0, word1, word2, and word3. data = lock register contents: pd(0) = secured silicon sector prot ection bit, pd(1) = persistent protection mode lock bit, pd(2 ) = password protection mode lock bit. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle, and the 4th, 5th, and 6th cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15-dq8 are don't cares for unlock and command cycles. 5. address bits a max :a16 are don't cares for unlock and command cycles, unless sa or pa required. (a max is the highest address pin.). 6. no unlock or command cycles required when reading array data. 7. the reset command is required to return to reading array data when device is in the autoselect mode, or if dq5 goes high (while the device is providing status data). 8. the fourth, fifth, and sixth cycle of the autoselect command sequence is a read cycle. 9. the data is 00h for an unprotected sector and 01h for a protected sector. see ?autoselect command sequence? for more information. this is same as ppb status read except that the protect and unprotect statuses are inverted here. 10. the data value for dq7 is ?1? for a serialized and protected otp region and ?0? for an unserialized and unprotected secured silicon sector region. see ?secured silicon sector flash memory region? for more information. for s29glxxxnh: xx18h/18h = not factory locked. xx98h/98h = factory locked. for s 29glxxxnl: xx08h/08h = not factory locked. xx88h/88h = factory locked. 11. command is valid when device is ready to read array data or when device is in autoselect mode. 12. the unlock-bypass command is required prior to the unlock-bypass-program command. 13. the unlock-bypass-reset command is required to return to reading array data when the device is in the unlock bypass mode. 14. the system may read and program/program suspend in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 15. the erase resume/program resume command is valid only during the erase suspend/program suspend modes. 16. issue this command sequence to return to read mode after detecting device is in a write-to-buffer-abort state. note: the full command sequence is required if resetting out of abort while using unlock bypass mode. 17. s29gl512nh/l = 2223h/23h, 2201h/01h; s29gl256nh/l = 2222h/22h, 2201h/01h; s29gl128nh/l = 2221h/21h, 2201h/ 01h. 18. the exit command returns the device to reading the array. 19. note that the password portion can be entered or read in any order as long as the entire 64-bit password is entered or read. 20. for pwdx, only one portion of the password can be programmed per each ?a0? command. 21. the all ppb erase command embeds progra mming of all ppb bits before erasure. 22. all lock register bits are one-time programmable. note that the program state = ?0? and the erase state = ?1?. also note that of both the persistent protection mode lock bit and the password protection mode lock bit cannot be programmed at the same time or the lock register bits program operation will abort and return the device to read mode. lock register bits that are reserved for future use will default to ?1's?. the lock register is shipped out as ?ffff's? before lock register bit progra m execution. 23. if any of the entry command was initiated, an exit command must be issued to reset the device into read mode. otherwise the device will hang. 24. if acc = v hh , sector protection will match when acc = v ih 25. protected state = ?00h?, unprotected state = ?01h?.
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 83 advance information write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. ta b l e 1 3 and the following subsec- tions describe the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. the device also provides a hardware-bas ed output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or has been completed. note that all write operation status dq bits are valid only after 4 s delay. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device outputs on dq7 the com- plement of the datum programmed to dq 7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a pro- gram address falls within a protected sector, data# polling on dq7 is active for approximately 1 s, then the device returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the device returns to the read mode. if not all selected sectors are protected, the em- bedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if the system reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is as- serted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq0?dq6 may be still invalid. valid data on dq0?dq7 will appear on successive read cycles. ta b l e 1 3 shows the outputs for data# polling on dq7. figure 5 shows the data# polling algorithm. figure 17 in the ac characteristics section shows the data# polling timing diagram.
84 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information figure 5. data# polling algorithm ry/ by# : read y/busy # the ry/by# is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. ta b l e 1 3 shows the outputs for ry/by#. dq7 = data? yes no no dq5 = 1 no yes yes fail pass read dq15?dq0 addr = va read dq15?dq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5.
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 85 advance information dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cy- cles to any address cause dq6 to toggle. the system may use either oe# or ce# to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algo- rithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is ac- tively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device en- ters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alter- natively, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protected sector, dq6 toggles for approxi- mately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. ta b l e 1 3 shows the outputs for toggle bit i on dq6. figure 6 shows the toggle bit algorithm. figure 18 in the ?ac characteristics? section shows the toggle bit tim- ing diagrams. figure 19 shows the differences between dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii.
86 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information figure 6. toggle bit algorithm dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe# or ce# to control the start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 twice read dq7?dq0 note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information.
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 87 advance information read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to ta b l e 1 3 to compare outputs for dq2 and dq6. figure 6 shows the toggle bit algorithm in flowchart form, and the section ?dq2: toggle bit ii? explains the algorithm. see also the ry/by#: ready/busy# subsec- tion. figure 18 shows the toggle bit timing diagram. figure 19 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 6 and figure 19 for the following discussion. whenever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase op- eration. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has suc- cessfully completed the program or erase operation. if it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as de- scribed in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algo- rithm when it returns to determine the status of the operation (top of figure 6 ). dq5: exceeded timing limits dq5 indicates whether the program, erase, or write-to-buffer time has ex- ceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the opera- tion, and when the timing limit has been exceeded, dq5 produces a ?1.? in all these cases, the system must write the reset command to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to de- termine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure,
88 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information the entire time-out also applies after each additional sector erase command. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between additional sector erase commands from the system can be as- sumed to be less than 50 s, the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept addi- tional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each sub- sequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. ta b l e 1 3 shows the status of dq3 relative to the other status bits. dq1: write-to-buffer abort dq1 indicates whether a write-to-buffer operation was aborted. under these conditions dq1 produces a ?1?. the system must issue the write-to-buffer-abort- reset command sequence to return the device to reading array data. see write buffer section for more details. ta b l e 1 3 . write operation status notes: 1. dq5 switches to ?1? when an embedded program, embedded erase, or write-to-buffer operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. the data# polling algorithm should be used to monitor the last loaded write-buffer address location. 4. dq1 switches to ?1? when the device has aborted the write-to-buffer operation. status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 ry/ by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 0 embedded erase algorithm 0 toggle 0 1 toggle n/a 0 program suspend mode program- suspend read program-suspended sector invalid (not allowed) 1 non-program suspended sector data 1 erase suspend mode erase- suspend read erase-suspended sector 1 no toggle 0 n/a toggle n/a 1 non-erase suspended sector data 1 erase-suspend-program (embedded program) dq7# toggle 0 n/a n/a n/a 0 write-to- buffer busy (note 3) dq7# toggle 0 n/a n/a 0 0 abort (note 4) dq7# toggle 0 n/a n/a 1 0
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 89 advance information absolute maximum ratings a9, oe#, and acc (note 5) . . . . . . . . . . . . . . . . . . . ?0.5 v to +12.5 v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . .?0.5 v to v cc + 0.5v 5. minimum dc input voltage on pins a9, oe#, and acc is operating ranges notes: 1. operating ranges define those limits between which the functionality of the device is guaranteed. 2. see ?product selector guide? section on page 19 . figure 7. figure 8. maximum positive overshoot waveform 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
90 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information dc characteristics cmos compatible-s29gl128n, s29gl256n, s29gl512n notes: 1. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 2. i cc active while embedded erase or embedded program or write buffer programming is in progress. 3. not 100% tested. 4. automatic sleep mode enables the lower power mode when addresses remain stable tor t acc + 30 ns. 5. v io = 1.65?1.95 v or 2.7?3.6 v 6. v cc = 3 v and v io = 3v or 1.8v. when v io is at 1.8v, i/o pins cannot operate at 3v. parameter symbol parameter description (notes) test conditions min typ max unit i li input load current (1) v in = v ss to v cc , v cc = v cc max wp/acc: 2.0 a others: 1.0 i lit a9 input load current v cc = v cc max ; a9 = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc active read current (1) ce# = v il, oe# = v ih , v cc = v ccmax , f = 5 mhz 30 50 ma ce# = v il , oe# = v ih , v cc = v ccmax , f = 10 mhz 60 90 i cc2 v cc intra-page read current (1) ce# = v il, oe# = v ih, v cc = v ccmax f = 10 mhz 110 ma ce# = v il , oe# = v ih , v cc = v ccmax , f=33 mhz 520 i cc3 v cc active erase/program current (2, 3) ce# = v il, oe# = v ih, v cc = v ccmax 50 80 ma i cc4 v cc standby current ce#, reset# = v ss 0.3 v, oe# = v ih , v cc = v ccmax v il = v ss + 0.3 v/- 0.1v 15ma i cc5 v cc reset current v cc = v ccmax ; v il = v ss + 0.3 v/-0.1v, reset# = v ss 0.3 v 15a i cc6 automatic sleep mode (4) v cc = v ccmax v ih = v cc 0.3 v, v il = v ss + 0.3 v/-0.1v, wp#/a cc = v ih 15a i acc acc accelerated program current ce# = v il, oe# = v ih, v cc = v ccmax, wp#/acc = v ih wp#/acc pin 10 20 ma v cc pin 50 80 v il input low voltage (5) ?0.1 0.3 x v io v v ih input high voltage (5) 0.7 x v io v io + 0.3 v v hh voltage for acc erase/program acceleration v cc = 2.7 ?3.6 v 11.5 12.5 v v id voltage for autoselect and temporary sector unprotect v cc = 2.7 ?3.6 v 11.5 12.5 v v ol output low voltage (5) i ol = 100 a 0.15 x v io v v oh output high voltage (5) i oh = -100 a 0.85 x v io v v lko low v cc lock-out voltage (3) 2.3 2.5 v
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 91 advance information test conditions note: if v io < v cc , the reference level is 0.5 v io . key to switching waveforms table 14. test specifications 2.7 k ? c l 6.2 k ? 3.3 v device under test note: diodes are in3064 or equivalent. figure 9. test setup test condition all speeds unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0?v io v input timing measurement reference levels (see note) 0.5v io v output timing measurement reference levels 0.5 v io v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) v io 0.0 v 0.5 v io 0.5 v io v output measurement level input note: if v io < v cc , the input measurement reference level is 0.5 v io . figure 10. input waveforms and measurement levels
92 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information ac characteristics read-only operations?s29gl128n, s29gl256n, s29gl512n notes: 1. not 100% tested. 2. ce#, oe# = v il 3. oe# = v il 4. see figure 9 and table 14 for test specifications. 5. unless otherwise indicated, ac specifications for 90 ns, 100 ns, and 110 ns speed options are tested with v io = v cc = 3 v. ac specifications for 110 ns speed options are tested with v io = 1.8 v and v cc = 3.0 v. parameter description test setup speed options jedec std. 90 100 110 110 unit t avav t rc read cycle time v io = v cc = 3 v min 90 100 110 ns v io = 1.8 v, v cc = 3 v 110 t avqv t acc address to output delay (note 2) v io = v cc = 3 v max 90 100 110 ns v io = 1.8 v, v cc = 3 v 110 t elqv t ce chip enable to output delay (note 3) v io = v cc = 3 v max 90 100 110 ns v io = 1.8 v, v cc = 3 v 110 t pacc page access time max 25 25 25 30 ns t glqv t oe output enable to output delay max 25 25 35 35 ns t ehqz t df chip enable to output high z (note 1) max 20 ns t ghqz t df output enable to output high z (note 1) max 20 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t ceh chip enable hold time read min 35 ns
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 93 advance information ac characteristics notes: 1. figure shows word mode. figure 12. page read timings figure 11. read operation timings t oh t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df t ceh amax - a2 ce# oe# a2 - a0* data bus same page aa ab ac ad qa qb qc qd t acc t pac c t pac c t pac c
94 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information ac characteristics hardware reset (reset#) notes: 1. not 100% tested. if ramp rate is equal to or faster than 1v /100s with a falling edge of the reset# pin initiated, the reset# pin needs to be held low only for 100s for power-up. 2. next generation devices may have different reset speeds. parameter description speed (note 2) unit jedec std. t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 ns t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s t rb ry/by# recovery time min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb t rh figure 13. reset timings
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 95 advance information ac characteristics erase and program operations ?s29gl128n, s29gl256n, s29gl512n notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specific ation is based upon a 16-word/32-byte write buffer operation. 5. unless otherwise indicated, ac specifications for 90 ns, 100 ns, and 110 ns speed options are tested with v io = v cc = 3 v. ac specifications for 110 ns speed options are tested with v io = 1.8 v and v cc = 3.0 v. parameter speed options jedec std. description 90 100 110 110 unit t avav t wc write cycle time (note 1) min 90 100 110 110 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 45 ns t whdx t dh data hold time min 0 ns t ceph ce# high during toggle bit polling min 20 t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 240 s effective write buffer program operation (notes 2, 4) per word typ s 15 accelerated effective write buffer program operation (notes 2, 4) per word typ s 13.5 program operation (note 2) word typ s 60 accelerated programming operation (note 2) word typ s 54 t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t vhh v hh rise and fall time (note 1) min 250 ns t vcs v cc setup time (note 1) min 50 s t busy erase/program valid to ry/by# delay min 90 ns
96 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information ac characteristics notes: 1. not 100% tested. 2. ce#, oe# = v il 3. oe# = v il 4. see figure 9 and table 14 for test specifications. oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa n otes: 1 . pa = program address, pd = program data, d out is the true data at the program address. 2 . illustration shows device in word mode. figure 14. program operation timings acc t vhh v hh v il or v ih v il or v ih t vhh figure 15. accelerated program timing diagram
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 97 advance information ac characteristics oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy notes: 1. sa = sector address (for sector erase), va = valid address for reading status data (. 2. these waveforms are for the word mode. figure 16. chip/sector erase operation timings
98 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information ac characteristics figure 17. data# polling timings (during embedded algorithms) we# ce# oe# high z t oe high z dq7 dq6?dq0 ry/by# t busy complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc note: 1. va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. 2. t oe for data polling is 45 ns when v io = 1.65 to 2.7 v and is 35 ns when v io = 2.7 to 3.6 v
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 99 advance information ac characteristics oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq2 and dq6 valid data valid status valid status valid status ry/by# note: va = valid address; not required for dq6. illust ration shows first two status cycle after command sequence, last status read cycle, and array data read cycle figure 18. toggle bit timings (during embedded algorithms) note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6 . figure 19. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
100 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information ac characteristics alternate ce# controlled erase and program operations- s29gl128n, s29gl256n, s29gl512n notes: 1. not 100% tested. 2. see the ?ac characteristics? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specific ation is based upon a 16-word/32-byte write buffer operation. 5. unless otherwise indicated, ac specifications for 90 ns, 100ns, and 110 ns speed options are tested with v io = v cc = 3 v. ac specifications for 110 ns speed options are tested with v io = 1.8 v and v cc = 3.0 v. parameter speed options jedec std. description 90 100 110 110 unit t avav t wc write cycle time (note 1) min 90 100 110 110 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t elax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dveh t ds data setup time min 45 ns t ehdx t dh data hold time min 0 ns t ceph ce# high during toggle bit polling min 20 ns t oeph oe# high during toggle bit polling min 20 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 35 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 2 40 s effective write buffer program operation (notes 2, 4) per word typ 15 s effective accelerated write buffer program operation (notes 2, 4) per word typ 13.5 s program operation (note 2) word typ 60 s accelerated programming operation (note 2) word typ 54 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec
december 15, 2004 s29glxxxn_mcp_a1 s29glxxxn mirrorbit tm flash family 101 advance information ac characteristics t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. 4. waveforms are for the word mode. figure 20. alternate ce# controlled write (erase/program) operation timings
102 s29glxxxn mirrorbit tm flash family s29glxxxn_mcp_a1 december 15, 2004 advance information erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25c, 3.0 v v cc , 10,000 cycles, checkerboard pattern. 2. under worst case conditions of 90c, v cc = 3.0 v, 100,000 cycles. 3. effective write buffer specification is ba sed upon a 16-word write buffer operation. 4. the typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maximum program times listed. 5. in the pre-programming step of the embedded erase algorithm, all bits are programmed to 00h before erasure. 6. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 12 for further information on command definitions. tsop pin and bga package capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. parameter typ (note 1) max (note 2) unit comments sector erase time 0.5 3.5 sec excludes 00h programming prior to erasure (note 5) chip erase time s29gl128n 64 256 sec s29gl256n 128 512 s29gl512n 256 1024 total write buffer programming time (note 3) 240 s excludes system level overhead (note 6) total accelerated effective write buffer programming time (note 3) 200 s chip program time s29gl128n 123 sec s29gl256n 246 s29gl512n 492 parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 tsop 6 7.5 pf bga 4.2 5.0 pf c out output capacitance v out = 0 tsop 8.5 12 pf bga 5.4 6.5 pf c in2 control pin capacitance v in = 0 tsop 7.5 9 pf bga 3.9 4.7 pf
october 4, 2004 cellram_00_a0 cellularram type 2 103 advance information cellularram type 2 128/64/32 megabit burst cellularram features ? single device supports asynchronous, page, and burst operations ? vcc voltages ? 1.70v?1.95v v cc ? random access time: 70ns ? burst mode write access ?continuous burst ? burst mode read access ? 4, 8, or 16 words, or continuous burst ? page mode read access ? sixteen-word page size ? interpage read access: 70ns ? intrapage read access: 20ns ? low power consumption ? asynchronous read < 25ma ? intrapage read < 15ma ? initial access, burst read < 35ma ? continuous burst read < 11ma ? standby: 180a ? deep power-down < 10a ? low-power features ? temperature compensated refresh (tcr) on-chip sensor control ? partial array refresh (par) ? deep power-down (dpd) mode general description cellularram? products are high-speed, cmos dynamic random access memories developed for low-power, portable applications. these devices include an industry standard burst mode flash interface that dramatically increases read/write band- width compared with other low-power sram or pseudo sram offerings. to operate smoothly on a burst flash bus, cellularram products incorporate a transparent self-refresh mechanism. the hidden refresh requires no additional support from the system memory controller and has no significant impact on de- vice read/write performance. two user-accessible control registers define device operation. the bus configura- tion register (bcr) defines how the cellularram device interacts with the system memory bus and is nearly identical to its counterpart on burst mode flash de- vices. the refresh configuration register (rcr) is used to control how refresh is performed on the dram array. these registers are automatically loaded with de- fault settings during power-up and can be updated anytime during normal operation. special attention has been focused on standby current consumption during self refresh. cellularram products include three mechanisms to minimize standby current. partial array refresh (par) enables the system to limit refresh to only
104 cellularram type 2 cellram_00_a0 october 4, 2004 advance information that part of the dram array that contains essential data. temperature compen- sated refresh (tcr) adjusts the refresh rate to match the device temperature? the refresh rate decreases at lower temperatures to minimize current consump- tion during standby. deep power-down (dpd) enables the system to halt the refresh operation altogether when no vital information is stored in the device. the system-configurable refresh mechanisms are accessed through the rcr. note: functional block diagrams illustrate simplified device operation. see truth table, ball descriptions, and timing di- agrams for detailed information. figure 21. functional block diagram 128m: a[22:0] 64m: a[21:0] 32m: a[20:0] input/ output mux and buffers control logic dram memory array ce# we# oe# clk adv# cre wait lb# ub# dq[7:0] dq[15:8] address decode logic refresh configuration register (rcr) bus configuration register (bcr)
october 4, 2004 cellram_00_a0 cellularram type 2 105 advance information note: the clk and adv# inputs can be tied to v ss if the device is always operating in asynchronous or page mode. wait will be asserted but should be ignored during asynchronous and page mode operations. ta b l e 1 5 . signal descriptions symbol type description 128m: a[22:0] 64m: a[21:0] 32m: a[20:0] input address inputs: inputs for addresses during read and write operations. addresses are internally latched during read and write cycles. the address lines are also used to define the value to be loaded into the bcr or the rcr. clk input clock: synchronizes the memory to the system operating frequency during synchronous operations. when configured for synchronous operation, the address is latched on the first rising clk edge when adv# is active. clk is static (high or low) during asynchronous access read and write operations and during page read access operations. adv# input address valid: indicates that a valid address is present on the address inputs. addresses can be latched on the rising edge of adv# during asynchronous read and write operations. adv# can be held low during asynchronous read and write operations. cre input configuration register enable: when cre is high, write operations load the rcr or bcr. ce# input chip enable: activates the device when low. when ce# is high, the device is disabled and goes into standby or deep power-down mode. oe# input output enable: enables the output buffers when low. when oe# is high, the output buffers are disabled. we# input write enable: determines if a given cycle is a write cycle. if we# is low, the cycle is a write to either a configuration register or to the memory array. lb# input lower byte enable. dq[7:0] ub# input upper byte enable. dq[15:8] dq[15:0] input/ output data inputs/outputs. wait output wait: provides data-valid feedback during burst read and write operations. the signal is gated by ce#. wait is used to arbitrate collisions between refresh and read/write operations. wait is asserted when a burst crosses a row boundary. wait is also used to mask the delay associated with opening a new internal page. wait is asserted and should be ignored during asynchronous and page mode operations. wait is high-z when ce# is high. v cc supply device power supply: (1.7v?1.95v) power supply for device core operation. v cc q supply i/o power supply: (1.7v?1.95v) power supply for input/output buffers. v ss supply v ss must be connected to ground. v ss q supply v ss q must be connected to ground.
106 cellularram type 2 cellram_00_a0 october 4, 2004 advance information notes: 1. clk may be high or low, but must be static during synchronous read, synchronous write, burst suspend, and dpd modes; and to achieve standby power during standby and active modes. 2. the wait polarity is configured through the bus configuration register (bcr[10]). 3. when lb# and ub# are in select mode (low), dq[15:0] are affected. when only lb# is in select mode, dq[7:0] are affected. when only ub# is in the select mode, dq[15:8] are affected. 4. the device will consume active power in this mode whenever addresses are changed. 5. when the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence. 6. v in = v cc q or 0v; all device balls must be static (unswitched) to achieve standby current. 7. dpd is maintained until rcr is reconfigured. ta b l e 1 6 . bus operations?asynchronous mode mode power clk ( note 1 ) adv# ce# oe# we# cre lb#/ ub# wait ( note 2 ) dq[15:0] ( note 3 )notes read active x l l l h l l low-z data-out 4 write active x l l x l l l low-z data-in 4 standby standby x x h x x l x high-z high-z 5 , 6 no operation idle x x l x x l x low-z x 4 , 6 configuration register active x llhlhxlow-zhigh-z dpd deep power-down x xhxxxxhigh-zhigh-z 7
october 4, 2004 cellram_00_a0 cellularram type 2 107 advance information notes: 1. clk may be high or low, but must be static during asynchronous read, synchronous write, burst suspend, and dpd modes; and to achieve standby power during standby and active modes. 2. the wait polarity is configured through the bus configuration register (bcr[10]). 3. when lb# and ub# are in select mode (low), dq[15:0] are affected. when only lb# is in select mode, dq[7:0] are affected. when only ub# is in the select mode, dq[15:8] are affected. 4. the device will consume active power in this mode whenever addresses are changed. 5. when the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence. 6. v in = v cc q or 0v; all device balls must be static (unswitched) to achieve standby current. 7. dpd is maintained until rcr is reconfigured. 8. burst mode operation is initialized through the bus configuration register (bcr[15]). functional description the cellularram bus interface supports both asynchronous and burst mode transfers. page mode accesses are also included as a bandwidth-enhancing ex- tension to the asynchronous read protocol. power-up initialization cellularram products include an on-chip voltage sensor used to launch the power-up initialization process. initialization will configure the bcr and the rcr with their default settings (see ta b l e 1 8 and ta b l e 2 2 ). v cc and v cc q must be applied simultaneously. when they reach a stable level at or above 1.7v, the de- vice will require 150s to complete its self-initialization process. during the initialization period, ce# should remain high. when initialization is complete, the device is ready for normal operation. ta b l e 1 7 . bus operations?burst mode mode power clk ( note 1 ) adv# ce# oe# we# cre lb#/ ub# wait ( note 2 ) dq[15:0] ( note 3 )notes async read active x l l l h l l low-z data-out 4 async write active x l l x l l l low-z data-in 4 standby standby x x h x x l x high-z high-z 5 , 6 no operation idle x x l x x l x low-z x 4 , 6 initial burst read active llxhlllow-zdata-out 4 , 8 initial burst write active l l h l l x low-z data-in 4 , 8 burst continue active hlxxlxlow-z data-in or data-out 4 , 8 burst suspend active x x l h x l x low-z high-z 4 , 8 configuration register active llhlhxlow-z high-z 8 dpd deep power-down x xh xxxxhigh-zhigh-z 7
108 cellularram type 2 cellram_00_a0 october 4, 2004 advance information bus operating modes cellularram products incorporate a burst mode interface found on flash products targeting low-power, wireless applications. this bus interface supports asynchro- nous, page mode, and burst mode read and write transfers. the specific interface supported is defined by the value loaded into the bcr. page mode is controlled by the refresh configuration register (rcr[7]). asynchronous mode cellularram products power up in the asynchronous operating mode. this mode uses the industry standard sram control bus (ce#, oe#, we#, lb#/ ub#). read operations ( figure 23 ) are initiated by bringing ce#, oe#, and lb#/ub# low while keeping we# high. valid data will be driven out of the i/os after the specified access time has elapsed. write operations ( figure 24 ) occur when ce#, we#, and lb#/ ub# are driven low. during asynchronous write opera- tions, the oe# level is a ?don't care,? and we# will override oe#. the data to be written is latched on the rising edge of ce#, we#, or lb#/ub# (whichever occurs first). asynchronous operations (page mode disabled) can either use the adv input to latch the address, or adv can be driven low during the entire read/ write operation. during asynchronous operation, the clk input must be held static (high or low, no transitions). wait will be driven while the device is enabled and its state should be ignored. figure 22. power-up initialization timing note: adv must remain low for page mode operation. figure 23. read operation (adv# low) v cc v cc q t pu > 150 s device initialization device ready for normal operation v cc = 1.7 v data valid address valid t rc = read cycle time ce# oe# we# address data lb#/ub# don't care
october 4, 2004 cellram_00_a0 cellularram type 2 109 advance information page mode read operation page mode is a performance-enhancing extension to the legacy asynchronous read operation. in page mode-capable products, an initial asynchronous read access is performed, then adjacent addresses can be read quickly by simply changing the low-order address. addresses a[3:0] are used to determine the members of the 16-address cellularram page. addresses a[4] and higher must remain fixed during the entire page mode access. figure 25 shows the timing for a page mode access. page mode takes advantage of the fact that adjacent ad- dresses can be read in a shorter period of time than random addresses. write operations do not include comparable page mode functionality. during asynchronous page mode operation, the clk input must be held low. ce# must be driven high upon completion of a page mode access. wait will be driven while the device is enabled and its state should be ignored. page mode is enabled by setting rcr[7] to high. write operations do not include comparable page mode functionality. adv must be driven low during all page mode read accesses. figure 24. write operation (adv# low) data valid address valid t wc = write cycle time ce# oe# we# address data lb#/ub# don't care
110 cellularram type 2 cellram_00_a0 october 4, 2004 advance information burst mode operation burst mode operations enable high-speed synchronous read and write opera- tions. burst operations consist of a multi-clock sequence that must be performed in an ordered fashion. after ce# goes low, the address to access is latched on the rising edge of the next clock that adv# is low. during this first clock rising edge, we# indicates whether the operation is going to be a read (we# = high, figure 26 ) or write (we# = low, figure 27 ). the size of a burst can be specified in the bcr either as a fixed length or contin- uous. fixed-length bursts consist of four, eight, or sixteen words. continuous bursts have the ability to start at a specified address and burst through the entire memory. the latency count stored in the bcr defines the number of clock cycles that elapse before the initial data value is transferred between the processor and cel- lularram device. the wait output asserts as soon as a burst is initiated, and de-asserts to indicate when data is to be transferred into (or out of) the memory. wait will again be asserted if the burst crosses a row boundary. once the cellularram device has restored the previous row's data and accessed the next row, wait will be deas- serted and the burst can continue (see figure 47 ). to access other devices on the same bus without the timing penalty of the initial latency for a new burst, burst mode can be suspended. bursts are suspended by stopping clk. clk can be stopped high or low. if another device will use the data bus while the burst is suspended, oe# should be taken high to disable the cellularram outputs; otherwise, oe# can remain low. note that the wait out- put will continue to be active, and as a result no other devices should directly share the wait connection to the controller. to continue the burst sequence, oe# is taken low, then clk is restarted after valid data is available on the bus. see ?how extended timings impact cellularram? operation? for restrictions on the maximum ce# low time during burst operations. if a burst suspension will figure 25. page mode read operation (adv# low) ce# oe# we# address data lb#/ub# don't care add[1] add[2] add[3] t aa d[0] t apa d[1] t apa d[2] t apa d[3] add[0]
october 4, 2004 cellram_00_a0 cellularram type 2 111 advance information cause ce# to remain low for longer than t cem , ce# should be taken high and the burst restarted with a new ce# low/adv# low cycle. note: non-default bcr settings: variable latency; latency code two (three clocks); wait active low; wait asserted during delay. figure 26. burst mode read (4-word burst) note: non-default bcr settings: variable latency; latency code two (three clocks); wait active low; wait asserted during delay. figure 27. burst mode write (4-word burst) don't care undefined legend: latency code 2 (3 clocks), variable d[0] d[1] d[2] d[3] read burst identified (we# = high) clk a[22:0] adv# ce# oe# we# wait dq[15:0] lb#/ub# address valid address valid latency code 2 (3 clocks), variable write burst identified (we# = low) clk a[22:0] adv# ce# oe# we# wait dq[15:0] lb#/ub# d[0] d[1] d[2] d[3] don't care legend:
112 cellularram type 2 cellram_00_a0 october 4, 2004 advance information mixed-mode operation the device can support a combination of synchronous read and asynchronous write operations when the bcr is configured for synchronous operation. the asynchronous write operation requires that the clock (clk) remain static (high or low) during the entire sequence. the adv# signal can be used to latch the target address, or it can remain low during the entire write operation. ce# can remain low when transitioning between mixed-mode operations with fixed la- tency enabled. note that the t cka period is the same as a read or write cycle. this time is required to ensure adequate refresh. mixed-mode operation facili- tates a seamless interface to legacy burst mode flash memory controllers. see figure 55 for the ?asynchronous write followed by burst read? timing diagram. wait operation the wait output on a cellularram device is typically connected to a shared, sys- tem-level wait signal (see figure 28 below). the shared wait signal is used by the processor to coordinate transactions with multiple memories on the synchro- nous bus. once a read or write operation has been initiated, wait goes active to indicate that the cellularram device requires additional time before data can be trans- ferred. for read operations, wait will remain active until valid data is output from the device. for write operations, wait will indicate to the memory control- ler when data will be accepted into the cellularram device. when wait transitions to an inactive state, the data burst will progress on successive clock edges. ce# must remain asserted during wait cycles (wait asserted and wait config- uration bcr[8] = 1). bringing ce# high during wait cycles may cause data corruption. (note that for bcr[8] = 0, the actual wait cycles end one cycle after wait de-asserts, and for row boundary crossings, start one cycle after the wait signal asserts.) when using variable initial access latency (bcr[14] = 0), the wait output per- forms an arbitration role for read or write operations launched while an on-chip refresh is in progress. if a collision occurs, the wait pin is asserted for additional clock cycles until the refresh has completed (see figure 29 and figure 30 ). when the refresh operation has completed, the read or write operation will continue normally. wait is also asserted when a continuous read or write burst crosses the boundary between 128-word rows. the wait assertion allows time for the new row to be accessed, and permits any pending refresh operations to be performed. wait will be asserted but should be ignored during asynchronous read and write, and page read operations. figure 28. wired or wait configuration cellularram external pull-up/ pull-down resistor processor ready other device wait other device wait wait
october 4, 2004 cellram_00_a0 cellularram type 2 113 advance information lb#/ub# operation the lb# enable and ub# enable signals support byte-wide data transfers. during read operations, the enabled byte(s) are driven onto the dqs. the dqs associ- ated with a disabled byte are put into a high-z state during a read operation. during write operations, any disabled bytes will not be transferred to the ram array and the internal value will remain unchanged. during an asynchronous write cycle, the data to be written is latched on the rising edge of ce#, we#, lb#, or ub#, whichever occurs first. when both the lb# and ub# are disabled (h igh) during an operation, the device will disable the data bus from receiving or transmitting data. although the device will seem to be deselected, it remains in an active mode as long as ce# remains low. note: non-default bcr settings: latency code two (three clocks); wait active low; wait asserted during delay. figure 29. refresh collision during read operation additional wait states inserted to allow refresh completion. clk a[22:0] adv# ce# oe# we# wait dq[15:0] lb#/ub# don't care undefined legend: v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il high-z v oh v ol d[0] d[1] d[2] d[3] v oh v ol address valid
114 cellularram type 2 cellram_00_a0 october 4, 2004 advance information low-power operation standby mode operation during standby, the device current consumption is reduced to the level necessary to perform the dram refresh operation. standby operation occurs when ce# is high. the device will enter a reduced power state upon completion of a read or write operation, or when the address and control inputs remain static for an extended period of time. this mode will continue until a change occurs to the address or control inputs. temperature compensated refresh temperature compensated refresh (tcr) is used to adjust the refresh rate de- pending on the device operating temperature. dram technology requires increasingly frequent refresh operation to maintain data integrity as tempera- tures increase. more frequent refresh is required due to increased leakage of the dram capacitive storage elements as temperatures rise. a decreased refresh rate at lower temperatures will facilitate a savings in standby current. tcr allows for adequate refresh at four different temperature thresholds (+15 c, +45 c, +70 c, and +85 c). the setting selected must be for a temperature higher than the case temperature of the cellularram device. for example, if the case temperature is 50 c, the system can minimize self refresh current con- sumption by selecting the +7 0c setting. the +15 c and +45 c settings would result in inadequate refreshing and cause data corruption. note: non-default bcr settings: latency code two (three clocks); wait active low; wait asserted during delay. figure 30. refresh collision during write operation address valid additional wait states inserted to allow refresh completion. clk a[22:0] adv# ce# oe# we# wait dq[15:0] lb#/ub# don't care legend: v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il high-z v oh v ol d[1] d[2] d[3] v oh v ol d[0]
october 4, 2004 cellram_00_a0 cellularram type 2 115 advance information partial array refresh partial array refresh (par) restricts refresh operation to a portion of the total memory array. this feature enables the device to reduce standby current by re- freshing only that part of the memory array required by the host system. the refresh options are full array, one-half array, one-quarter array, three-quarter ar- ray, or none of the array. the mapping of these partitions can start at either the beginning or the end of the address map (see ta b l e 2 3 ). read and write oper- ations to address ranges receiving refresh will not be affected. data stored in addresses not receiving refresh will become corrupted. when re-enabling addi- tional portions of the array, the new portions are available immediately upon writing to the rcr. deep power-down operation deep power-down (dpd) operation disables all refresh-related activity. this mode is used if the system does not require the storage provided by the cellularram device. any stored data will become corrupted when dpd is enabled. when re- fresh activity has been re-enabled by rewriting the rcr, the cellularram device will require 150s to perform an initialization procedure before normal operations can resume. during this 150s period, the current consumption will be higher than the specified standby levels, but considerably lower than the active current specification. dpd cannot be enabled or disabled by writing to the rcr using the software ac- cess sequence; the rcr should be accessed using cre instead. configuration registers two user-accessible configuration registers define the device operation. the bus configuration register (bcr) defines how the cellularram interacts with the sys- tem memory bus and is nearly identical to its counterpart on burst mode flash devices. the refresh configuration register (rcr) is used to control how refresh is performed on the dram array. these registers are automatically loaded with default settings during power-up, and can be updated any time the devices are operating in a standby state. access using cre the configuration registers can be written to using either a synchronous or an asynchronous operation when the configur ation register enable (cre) input is high (see figure 31 and figure 32 ). when cre is low, a read or write oper- ation will access the memory array. the register values are written via address pins a[21:0]. in an asynchronous write, the values are latched into the config- uration register on the rising edge of adv#, ce#, or we#, whichever occurs first; lb# and ub# are ?don?t care.? the bcr is accessed when a[19] is high; the rcr is accessed when a[19] is low. for reads, address inputs other than a[19] are ?don?t care,? and register bits 15:0 are output on dq[15:0].
116 cellularram type 2 cellram_00_a0 october 4, 2004 advance information note: a[19] = low to load rcr; a[19] = high to load bcr. figure 31. configuration register write, asynchronous mode followed by read select control register opcode address t avs t avh address t avs t avh t vph t vp t cbph initiate control register access t cw t wp write address bus value to control register data valid don't care legend: a[22:0] (except a19) a19 (note) cre adv# ce# oe# we# lb#/ub# dq[15:0]
october 4, 2004 cellram_00_a0 cellularram type 2 117 advance information bus configuration register the bcr defines how the cellularram device interacts with the system memory bus. page mode operation is enabled by a bit contained in the rcr. ta b l e 1 8 below describes the control bits in the bcr. at power up, the bcr is set to 9d4fh. notes: 1. non-default bcr settings: latency code two (three clocks); wait active low; wait asserted during delay. 2. a[19] = low to load rcr; a[19] = high to load bcr. 3. ce# mu st r ema in low to complete a bur st-of-one write. wait mu st be monitored? addition al wait cycles ca used by refresh collisions require a corresponding number of additional ce# low cycles. figure 32. configuration register write, synchronous mode followed by read0 latch control register value address address t hd opcode t sp latch control register address t sp t hd t sp t hd t csp t cbph (note 3) high-z high-z t cew data valid clk a[22:0] (except a19) a19 (note 2) cre adv# ce# oe# we# lb#/ub# wait dq[15:0] don't care legend: t sp t hd
118 cellularram type 2 cellram_00_a0 october 4, 2004 advance information the bcr is accessed using cre and a[19] high. ta b l e 1 8 . bus configuration register definition note: burst wrap and length apply to read operations only. a13 11 0 latency counter initial latency 321 wait polarity 4 5 6 7 8 output impedance burst wrap (bw) (note) 14 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 output impedance full drive (default) 1/2 drive 1/4 drive reserved bcr[5] 0 0 1 1 bcr[4] 0 1 0 1 15 burst length (bl) (note) reserved reserved 9 10 operating mode 0 1 wait polarity active low active high (default) bcr[10] reserved 22?20 a14 a15 a[18:16] 19 18?16 register select reserved a19 a[22:20] reserved must be set to "0" must be set to "0" all must be set to "0" 0 1 operating mode synchronous burst access mode asynchronous access mode (default) bcr[15] 0 1 register select select rcr select bcr bcr[19] burst wrap (note) burst wraps within the burst length burst no wrap (default) bcr[3] 0 1 must be set to "0" setting is ignored wait configuration (wc) 12 13 bcr[12] bcr[11] latency counter bcr[13] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 code 0?reserved code 1?reserved code 2 code 3 (default) code 4 code 5 code 6 code 7?reserved 0 1 wait configuration asserted during delay asserted one data cycle before delay (default) bcr[8] bcr[1] bcr[0] burst length (note) bcr[2] 0 0 0 1 0 1 1 1 1 0 1 1 4 words 8 words 16 words continuous burst (default) reserved must be set to "0" others
october 4, 2004 cellram_00_a0 cellularram type 2 119 advance information burst length (bcr[2:0]): default = continuous burst burst lengths define the number of words the device outputs during burst read operations. the device supports a burst leng th of 4, 8, or 16 words. the device can also be set in continuous burst mode where data is accessed sequentially without regard to address boundaries. enabling burst no-wrap with bcr[3] = 1 overrides the burst-length setting. burst wrap (bcr[3]): default = no wrap the burst-wrap option determines if a 4-, 8-, or 16-word read burst wraps within the burst length or steps through sequential addresses. if the wrap option is not enabled, the device accesses data from sequential addresses without regard to burst boundaries. when continuous burst operation is selected, the internal ad- dress wraps to 000000h if the burst goes past the last address. enabling burst nowrap (bcr[3] = 1) overrides the burst-length setting. ta b l e 1 9 . sequence and burst length burst wrap starting address 4-word burst length 8-word burst length 16-word burst length continuous burst bcr[3] wrap (decimal) linear linear linear linear 0yes 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-3-4-5-6-? 1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 1-2-3-4-5-6-7-? 2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 2-3-4-5-6-7-8-? 3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 3-4-5-6-7-8-9-? 4 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 4-5-6-7-8-9-10-? 5 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 5-6-7-8-9-10-11-? 6 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 6-7-8-9-10-11-12-? 7 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 7-8-9-10-11-12-13-? ? ? ? 14 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 14-15-16-17-18-19-20-? 15 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 15-16-17-18-19-20-21? 1no 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-3-4-5-6-? 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16 1-2-3-4-5-6-7-? 2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17 2-3-4-5-6-7-8-? 3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18 3-4-5-6-7-8-9-? 4 4-5-6-7-8-9-10-11 4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19 4-5-6-7-8-9-10-? 5 5-6-7-8-9-10-11-12 5-6-7-8-9-10-11-12-13-?-15-16-17-18-19-20 5-6-7-8-9-10-11? 6 6-7-8-9-10-11-12-13 6-7-8-9-10-11-12-13-14-?-16-17-18-19-20-21 6-7-8-9-10-11-12? 7 7-8-9-10-11-12-13-14 7-8-9-10-11-12-13-14-?-17-18-19-20-21-22 7-8-9-10-11-12-13? ? ? ? 14 14-15-16-17-18-19-?-23-24-25-26-27-28-29 14-15-16-17-18-19-20-? 15 5-16-17-18-19-20-?-24-25-26-27-28-29-30 15-16-17-18-19-20-21-?
120 cellularram type 2 cellram_00_a0 october 4, 2004 advance information output impedance (bcr[5:4]): default = outputs use full drive strength the output driver strength can be altered to full, one-half, or one-quarter strength to adjust for different data bus loading scenarios. the reduced-strength options are intended for stacked chip (flash + cellularram) environments when there is a dedicated memory bus. the reduced-drive-strength option minimizes the noise generated on the data bus during read operations. normal output drive strength should be selected when using a discrete cellularram device in a more heavily loaded data bus environment. outputs are configured at full drive strength during testing. wait configuration (bcr[8]): default = wait transitions one clock before data valid/invalid the wait configuration bit is used to determine when wait transitions between the asserted and the de-asserted state with respect to valid data presented on the data bus. the memory controller will use the wait signal to coordinate data transfer during synchronous read and write operations. when bcr[8] = 0, data will be valid or invalid on the clock edge immediately after wait transitions to the de-asserted or asserted state, respectively ( figure 33 and figure 35 ). when a8 = 1, the wait signal transitions one clock period prior to the data bus going valid or invalid ( figure 34 ). wait polarity (bcr[10]): default = wait active high the wait polarity bit indicates whether an asserted wait output should be high or low. this bit will determine whether th e wait signal requires a pull-up or pull- down resistor to maintain the de-asserted state. ta b l e 2 0 . output impedance bcr[5] bcr[4] drive strength 00 full 01 1/2 10 1/4 11reserved note: data valid/invalid immediately after wait transitions (bcr[8] = 0). see figure 35 . figure 33. wait configuration (bcr[8] = 0) data[0] data[1] high-z clk wait dq[15:0] data immediately valid (or invalid)
october 4, 2004 cellram_00_a0 cellularram type 2 121 advance information latency counter (bcr[13:11]): default = three-clock latency the latency counter bits determine how many clocks occur between the begin- ning of a read or write operation and the first data value transferred. latency codes from two (three clocks) to six (seven clocks) are allowed (see ta b l e 2 1 and figure 36 below). note: latency is the number of clock cycles from the initiation of a burst operation until data appears. data is trans- ferred on the next clock cycle. note: valid/invalid data delayed for one clock after wait transitions (bcr[8] = 1). see figure 35 . figure 34. wait configuration (bcr[8] = 1) note: non-default bcr setting: wait active low. figure 35. wait configuration during burst operation ta b l e 2 1 . variable latency configuration codes bcr[13:11] latency configuration code latency (note) max input clk frequency (mhz) normal refresh collision 70ns/80 mhz 85ns/66 mhz 010 2 (3 clocks) 2 4 75 (13.0ns) 44 (22.7ns) 011 3 (4 clocks)?default 3 6 80 (12.5ns) 66 (15.2ns) 100 4 (5 clocks) 4 8 data[0] high-z clk wait dq[15:0] data valid (or invalid) after one clock delay d[0] d[1] d[2] d[3] d[4] clk wait wait dq[15:0] bcr[8] = 0 data valid in current cycle bcr[8] = 1 data valid in next cycle don't care legend:
122 cellularram type 2 cellram_00_a0 october 4, 2004 advance information operating mode (bcr[15]): default = asynchronous operation the operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation. refresh configuration register the refresh configuration register (rcr) defines how the cellularram device per- forms its transparent self refresh. altering the refresh parameters can dramatically reduce current consumption during standby mode. page mode con- trol is also embedded into the rcr. ta b l e 2 2 below describes the control bits used in the rcr. at power-up, the rcr is set to 0070h. the rcr is accessed using cre and a[19] low. figure 36. latency counter (variable initial latency, no refresh collision) code 2 valid output valid output valid output valid output valid address valid output code 3 (default) valid output valid output valid output valid output code 4 valid output valid output valid output v ih v il v ih v il v ih v il v oh v ol v oh v ol v oh v ol clk a[21:0] adv# a/dq[15:0] a/dq[15:0] a/dq[15:0] don't care undefined legend:
october 4, 2004 cellram_00_a0 cellularram type 2 123 advance information partial array refresh (rcr[2:0]): default = full array refresh the par bits restrict refresh operation to a portion of the total memory array. this feature allows the device to reduce standby current by refreshing only that part of the memory array required by the host system. the refresh options are full ar- ray, one-half array, one-quarter array, three-quarters array, or none of the array. the mapping of these partitions can start at either the beginning or the end of the address map (see ta b l e 2 3 through ta b l e 2 5 ). table 22. refresh configuration register mapping ta b l e 2 3 . 128mb address patterns for par (rcr[4] = 1) rcr[2] rcr[1] rcr[0] active section address space size density 0 0 0 full die 000000h?7fffffh 8 meg x 16 128mb 0 0 1 one-half of die 000000h?3fffffh 4 meg x 16 64mb 0 1 0 one-quarter of die 000000h?1fffffh 2 meg x 16 32mb 0 1 1 one-eighth of die 000000h?0fffffh 1 meg x 16 16mb 1 0 0 none of die 0 0 meg x 16 0mb 1 0 1 one-half of die 400000h?7fffffh 4 meg x 16 64mb 1 1 0 one-quarter of die 600000h?7fffffh 2 meg x 16 32mb 1 1 1 one-eighth of die 700000h?7fffffh 1 meg x 16 16mb par a4 a3 a2 a1 a0 read configuration register address bus a5 a6 all must be set to "0" 0 1 deep power-down dpd enable dpd disable (default) rcr[4] a[18:8] register select reserved reserved reserved tcr a[22:20] a19 0 1 register select select rcr select bcr rcr[19] all must be set to "0" rcr[1] rcr[0] refresh coverage rcr[2] 0 0 full array (default) 0 0 1 bottom 1/2 array 0 1 0 bottom 1/4 array 0 1 1 bottom 1/8 array 0 01 1 top 1/2 array 10 1 top 1/4 array dpd must be set to "0" a7 page 0 1 page mode enable/disable page mode disabled (default) page mode enable rcr[7] 4 51 2 30 6 18?8 19 22?20 7 1 none of array 00 1 top 3/4 array 11 rcr[6] rcr[5] maximum case temp +85oc (default) 11 00 01 10 +70oc +45oc +15oc
124 cellularram type 2 cellram_00_a0 october 4, 2004 advance information deep power-down (rcr[4]): default = dpd disabled the deep power-down bit enables and disables all refresh-related activity. this mode is used if the system does not require the storage provided by the cellular- ram device. any stored data will become corrupted when dpd is enabled. when refresh activity has been re-enabled, the cellularram device will require 150s to perform an initialization procedure before normal operations can resume. deep power-down is enabled when rc r[4] = 0, and remains enabled until rcr[4] is set to ?1.? temperature compensated refresh (rcr[6:5]): default = +85oc operation the tcr bits allow for adequate refresh at four different temperature thresholds (+15oc, +45oc, +70oc, and +85oc). the setting selected must be for a temper- ature higher than the case temperature of the cellurlarram device. if the case temperature is +50oc, the system can minimize self refresh current consumption by selecting the +70oc setting. the +15oc and +45oc settings would result in inadequate refreshing and cause data corruption. page mode operation (rcr[7]): default = disabled the page mode operation bit determines whether page mode is enabled for asyn- chronous read operations. in the power-up default state, page mode is disabled. ta b l e 2 4 . 64mb address patterns for par (rcr[4] = 1) rcr[2] rcr[1] rcr[0] active section address space size density 0 0 0 full die 000000h?3fffffh 4 meg x 16 64mb 0 0 1 one-half of die 000000h?2fffffh 3 meg x 16 48mb 0 1 0 one-quarter of die 000000h?1fffffh 2 meg x 16 32mb 0 1 1 one-eighth of die 000000h?0fffffh 1 meg x 16 16mb 1 0 0 none of die 0 0 meg x 16 0mb 1 0 1 one-half of die 100000h?3fffffh 3 meg x 16 48mb 1 1 0 one-quarter of die 200000h?3fffffh 2 meg x 16 32mb 1 1 1 one-eighth of die 300000h?3fffffh 1 meg x 16 16mb ta b l e 2 5 . 32mb address patterns for par (rcr[4] = 1) rcr[2] rcr[1] rcr[0] active section address space size density 0 0 0 full die 000000h?1fffffh 2 meg x 16 32mb 0 0 1 one-half of die 000000h?17ffffh 1.5 meg x 16 24mb 0 1 0 one-quarter of die 000000h?0fffffh 1 meg x 16 16mb 0 1 1 one-eighth of die 000000h?07ffffh 512k x 16 8mb 1 0 0 none of die 0 0 meg x 16 0mb 1 0 1 one-half of die 080000h?1fffffh 1.5 meg x 16 24mb 1 1 0 one-quarter of die 100000h?1fffffh 1 meg x 16 16mb 1 1 1 one-eighth of die 180000h?1fffffh 512k x 16 8mb
october 4, 2004 cellram_00_a0 cellularram type 2 125 advance information absolute maximum ratings voltage to any ball except v cc , v cc q relative to v ss . . . . . -0.50v to (4.0v or v cc q + 0.3v, whichever is less) voltage on v cc supply relative to v ss . . . . . . . . . . . . . . . . -0.2v to +2.45v voltage on v cc q supply relative to v ss . . . . . . . . . . . . . . . . -0.2v to +2.45v storage temperature (plastic) . . . . . . . . . . . . . . . . . . . . . . -55oc to +150oc operating temperature (case) wireless. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25oc to +85oc *stresses greater than those listed may ca use permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
126 cellularram type 2 cellram_00_a0 october 4, 2004 advance information dc characteristics notes: 1. wireless temperature (-25oc < tc < +85oc); industrial temperature (-40oc < tc < +85oc). 2. input signals may overshoot to v cc q + 1.0v for periods less than 2ns during transitions. 3. input signals may undershoot to v ss - 1.0v for periods less than 2ns during transitions. 4. bcr[5:4] = 00b. 5. this parameter is specified with the outputs disabled to avoid external loading effects. the user must add the current required to drive output capaci tance expected in the actual system. 6. isb (max) values measured with par set to full array and tcr set to +85c. to achieve low standby current, all inputs must be driven to either v cc q or v ss . ta b l e 2 6 . electrical characteristics and operating conditions description conditions symbol min max units notes supply voltage v cc 1.70 1.95 v i/o supply voltage v cc q w: 1.8v 1.70 1.95 v j: 1.5v 1.35 1.65 v input high voltage v ih v cc q - 0.4 v cc q + 0.2 v 2 input low voltage v il -0.20 0.4 v 3 output high voltage i oh = -0.2ma v oh 0.80 v cc qv 4 output low voltage i ol = +0.2ma v ol 0.20 v cc qv 4 input leakage current v in = 0 to v cc qi li 1a output leakage current oe# = v ih or chip disabled i lo 1a operating current asynchronous random read v in = v cc q or 0v chip enabled, iout = 0 i cc 1 -70 25 ma 5 -85 20 asynchronous page read -70 15 -85 12 initial access, burst read v in = v cc q or 0v chip enabled, iout = 0 i cc 1 80 mhz 35 ma 5 66 mhz 30 continuous burst read 80 mhz 18 66 mhz 15 write operating current v in = v cc q or 0v chip enabled i cc 2 -70 25 ma -85 20 standby current v in = v cc q or 0v ce# = v cc q i sb 128 m 180 a 6 64 m 120 32 m 110
october 4, 2004 cellram_00_a0 cellularram type 2 127 advance information note: i par (max) values measured with tcr set to 85c. ta b l e 2 8 . partial array refresh specifications and conditions note:i par (max) values measured with tcr set to 85c. ta b l e 2 7 . temperature compensated refresh specifications and conditions description conditions symbol density max case te m p e r a t u r e standard power (no desig.) units temperature compensated refresh standby current v in = v cc q or 0v, ce# = v cc q i tcr 64 mb +85 c120 a +70 c105 +45 c85 +15 c70 32 mb +85 c110 +70 c95 +45 c80 +15 c70 description conditions symbol density array partition standard power (no desig.) units partially array refresh standby current v in = v cc q or 0v, ce# = v cc q i par 64 mb full 120 a 1/2 115 1/4 110 1/8 105 070 32 mb full 110 1/2 105 1/4 100 1/8 95 070 128 mb full 180 050 ta b l e 2 9 . deep power-down specifications description conditions symbol typ units deep power-down v in = v cc q or 0v; +25c; v cc = 1.8v i zz 10 a
128 cellularram type 2 cellram_00_a0 october 4, 2004 advance information ac characteristics notes: 1. ac test inputs are driven at v cc q for a logic 1 and v ss for a logic 0. input rise and fall times (10% to 90%) < 1.6ns. 2. input timing begins at v cc q/2. 3. output timing ends at v cc q/2. figure 37. ac input/output reference waveform note: all tests are performed with the outputs configured for full drive strength (bcr[5] = 0). figure 38. output load circuit ta b l e 3 0 . output load circuit v cc qr1/r2 1.8v 2.7k ? output test points input (note 1) v cc q v ss v cc q /2 (note 2) v cc q/2 (note 3) dut v cc q r1 r2 30pf test point
october 4, 2004 cellram_00_a0 cellularram type 2 129 advance information notes: 1. all tests are performed with the outputs configured for full drive strength (bcr[5] = 0). 2. see ?how extended timings impact cellularram? operation? below. 3. high-z to low-z timings are tested with the circuit shown in figure 38 . the low-z timings measure a 4. 100mv transition away from the high-z (v cc q/2) level toward either v oh or v ol . 5. low-z to high-z timings are tested with the circuit shown in figure 38 . the high-z timings measure a 100mv transition from either v oh or v ol toward v cc q/2. ta b l e 3 1 . asynchronous read cycle timing requirements parameter symbol 85ns/66 mhz 70ns/80 mhz units notes minmaxminmax address access time t aa 85 70 ns adv# access time t aadv 85 70 ns page access time t apa 25 20 ns address hold from adv# high t avh 55ns address setup to adv# high t avs 10 10 ns lb#/ub# access time t ba 85 70 ns lb#/ub# disable to dq high-z output t bhz 88ns4 lb#/ub# enable to low-z output t blz 10 10 ns 3 ce# high between subsequent mixed-mode operations t cbph 55ns maximum ce# pulse width t cem 44s2 ce# low to wait valid t cew 1 7.5 1 7.5 ns chip select access time t co 85 70 ns ce# low to adv# high t cvs 10 10 ns chip disable to dq and wait high-z output t hz 88ns4 chip enable to low-z output t lz 10 10 ns 3 output enable to valid output t oe 20 20 ns output hold from address change t oh 55ns output disable to dq high-z output t ohz 88ns4 output enable to low-z output t olz 55ns3 page cycle time t pc 25 20 ns read cycle time t rc 85 70 ns adv# pulse width low t vp 10 10 ns adv# pulse width high t vph 10 10 ns
130 cellularram type 2 cellram_00_a0 october 4, 2004 advance information notes: 1. all tests are performed with the outputs configured for full drive strength (bcr[5] = 0). 2. low-z to high-z timings are tested with the circuit shown in figure 38 . the high-z timings measure a 100mv transition from either v oh or v ol toward v cc q/2. 3. high-z to low-z timings are tested with the circuit shown in figure 38 . the low-z timings measure a 100mv transition away from the high-z (v cc q/2) level toward either v oh or v ol . ta b l e 3 2 . burst read cycle timing requirements parameter symbol 70ns/80 mhz 85ns/66 mhz units notes min max min max burst to read access time (variable latency) t aba 35 55 ns clk to output delay t aclk 911ns address setup to adv# high t avs 10 10 ns burst oe# low to output delay t boe 20 20 ns ce# high between subsequent mixed-mode operations t cbph 55ns ce# low to wait valid t cew 17.517.5ns clk period t clk 12.5 15 ns ce# setup time to active clk edge t csp 45ns hold time from active clk edge t hd 22ns chip disable to dq and wait high-z output t hz 88ns2 clk rise or fall time t khkl 1.6 1.6 ns clk to wait valid t khtl 911ns clk to dq high-z output t khz 3838ns clk to low-z output t klz 2525ns output hold from clk t koh 22ns clk high or low time t kp 33ns output disable to dq high-z output t ohz 88ns2 output enable to low-z output t olz 55ns3 setup time to active clk edge t sp 33ns
october 4, 2004 cellram_00_a0 cellularram type 2 131 advance information notes: 1. see ?how extended timings impact cellularram? operation? below. 2. low-z to high-z timings are tested with the circuit shown in figure 38 . the high-z timings measure a 100mv transition from either v oh or v ol toward v cc q/2. 3. high-z to low-z timings are tested with the circuit shown in figure 38 . the low-z timings measure a 100mv transition away from the high-z (v cc q/2) level toward either v oh or v ol . table 33. asynchronous write cycle timing requirements parameter symbol 70ns/80 mhz 85ns/66 mhz units notes min max min max address and adv# low setup time t as 00ns address hold from adv# going high t avh 55ns address setup to adv# going high t avs 10 10 ns address valid to end of write t aw 70 85 ns lb#/ub# select to end of write t bw 70 85 ns maximum ce# pulse width t cem 44s1 ce# low to wait valid t cew 17.517.5ns async address-to-burst transition time t cka 70 85 ns ce# low to adv# high t cvs 10 10 ns chip enable to end of write t cw 70 85 ns data hold from write time t dh 00ns data write setup time t dw 23 23 ns 1 chip disable to wait high-z output t hz 88ns chip enable to low-z output t lz 10 10 ns 3 end write to low-z output t ow 55ns3 adv# pulse width t vp 10 10 ns adv# pulse width high t vph 10 10 ns adv# setup to end of write t vs 70 85 ns write cycle time t wc 70 85 ns write to dq high-z output t whz 88ns2 write pulse width t wp 46 55 ns 1 write pulse width high t wph 10 10 ns write recovery time t wr 00ns ta b l e 3 4 . burst write cycle timing requirements parameter symbol 70ns/80 mhz 85ns/66 mhz units notes min max min max ce# high between subsequent mixed-mode operations t cbph 55ns ce# low to wait valid t cew 17.517.5ns
132 cellularram type 2 cellram_00_a0 october 4, 2004 advance information timing diagrams clock period t clk 12.5 15 ns ce# setup to clk active edge t csp 45ns hold time from active clk edge t hd 22ns chip disable to wait high-z output t hz 88ns clk rise or fall time t khkl 1.6 1.6 ns clock to wait valid t khtl 911ns clk high or low time t kp 33ns setup time to activate clk edge t sp 33ns figure 39. initialization period ta b l e 3 5 . initialization timing parameters parameter symbol 70ns/80 mhz 85ns/66 mhz units notes minmaxminmax initialization period (required before normal operations) t pu 150 150 s table 34. burst write cycle timing requirements (continued) parameter symbol 70ns/80 mhz 85ns/66 mhz units notes min max min max t pu v cc , v cc q = 1.7v v cc (min) device ready fo r normal operation
october 4, 2004 cellram_00_a0 cellularram type 2 133 advance information figure 40. asynchronous read ta b l e 3 6 . asynchronous read timing parameters symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t aa 70 85 ns t ba 70 85 ns t bhz 88ns t blz 10 10 ns t cbph 55ns t olz t oe t lz t blz t ba t co t hz t aa high-z high-z t bhz t rc t ohz don't care undefined legend: valid address t cbph valid output t hz t cew high-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il a[22:0] adv# ce# lb#/ub# oe# we# dq[15:0] wait
134 cellularram type 2 cellram_00_a0 october 4, 2004 advance information t cew 17.517.5ns t co 70 ns t hz 88ns t lz 10 10 ns t oe 20 20 ns t ohz 88ns t olz 55ns t rc 70 85 ns table 36. asynchronous read timing parameters (continued) symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax
october 4, 2004 cellram_00_a0 cellularram type 2 135 advance information figure 41. asynchronous read using adv# ta b l e 3 7 . asynchronous read timing parameters using adv# symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t aa 70 85 ns t aadv 70 85 ns t olz t oe t lz t blz t ba t co t hz t aa high-z high-z t bhz t ohz don't care undefined legend: valid address t cbph valid output t hz t cew high-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il a[22:0] adv# ce# lb#/ub# oe# we# dq[15:0] wait t vph t avs t avh t cvs t vp t aadv
136 cellularram type 2 cellram_00_a0 october 4, 2004 advance information t cvs 10 10 ns t avh 55ns t avs 10 10 ns t ba 70 85 ns t bhz 88ns t blz 10 10 ns t cbph 55ns t cew 17.517.5ns t co 70 85 ns t cvs 10 10 ns t hz 88ns t lz 10 10 ns t oe 20 20 ns t ohz 88ns t olz 55ns t vp 10 10 ns t vph 10 10 ns table 37. asynchronous read timing parameters using adv# (continued) symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax
october 4, 2004 cellram_00_a0 cellularram type 2 137 advance information figure 42. page mode read ta b l e 3 8 . asynchronous read timing parameters?page mode operation symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t aa 70 85 ns t apa 20 25 ns t ba 70 85 ns t bhz 88ns t olz t oe t lz t blz t ba t hz t aa high-z high-z t bhz t ohz don't care undefined legend: t cbph t hz t cew high-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il a[22:0] adv# ce# lb#/ub# oe# we# dq[15:0] wait t pc t cem t co t rc t cbph valid address v ih v il a[3:0] valid address valid address valid address valid address t apa t oh valid output valid output valid output valid output
138 cellularram type 2 cellram_00_a0 october 4, 2004 advance information t blz 10 10 ns t cbph 55ns t cem 44s t cew 17.517.5ns t co 70 85 ns t hz 88ns t lz 10 10 ns t oe 20 20 ns t oh 55ns t ohz 88ns t olz 55ns t pc 20 25 ns t rc 70 85 ns table 38. asynchronous read timing parameters?page mode operation (continued) symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax
october 4, 2004 cellram_00_a0 cellularram type 2 139 advance information note: non-default bcr settings: latency code two (three clocks); wait active low; wait asserted during delay. figure 43. single-access burst read operation?variable latency ta b l e 3 9 . burst read timing parameters?single access, variable latency symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t aba 35 55 ns t aclk 911ns t ohz t olz t aclk t koh t hz high-z high-z don't care undefined legend: valid address valid output t khtl t cew high-z v ih v il v ih v il v ih v il v ih v il v ih v il a[22:0] adv# ce# lb#/ub# v oh v ol v oh v ol dq[15:0] wait t sp t clk t csp t boe t aba t khkl t kp t kp v ih v il clk t sp t hd t hd t hd v ih v il oe# we# t sp t hd t sp t hd read burst identified ( we# = high )
140 cellularram type 2 cellram_00_a0 october 4, 2004 advance information t boe 20 20 ns t cew 17.517.5ns t clk 12.5 15 ns t csp 45ns t hd 22ns t hz 88ns t khkl 1.6 1.6 ns t khtl 911ns t koh 22ns t kp 33ns t ohz 88ns t olz 55ns t sp 33ns table 39. burst read timing parameters?single access, variable latency (continued) symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax
october 4, 2004 cellram_00_a0 cellularram type 2 141 advance information note: non-default bcr settings: latency code two (three clocks); wait active low; wait asserted during delay. figure 44. four-word burst read operation?variable latency t ohz t olz high-z high-z t cbph don't care undefined legend: t cew high-z v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol a[22:0] adv# ce# lb#/ub# dq[15:0] wait t sp t csp t boe t aba t sp t hd t hd v ih v il oe# we# t sp t hd t sp t hd read burst identified ( we# = high ) valid address t clk t khkl t kp t kp v ih v il clk t hd t hz valid output valid output valid output valid output t khtl t koh t aclk
142 cellularram type 2 cellram_00_a0 october 4, 2004 advance information ta b l e 4 0 . burst read timing parameters?4-word burst symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t aba 35 55 ns t aclk 911ns t boe 20 20 ns t cbph 55ns t cew 17.517.5ns t clk 12.5 15 ns t csp 45ns t hd 22ns t hz 88ns t khkl 1.6 1.6 ns t khtl 911ns t koh 22ns t kp 33ns t ohz 88ns t olz 55ns t sp 33ns
october 4, 2004 cellram_00_a0 cellularram type 2 143 advance information note: non-default bcr settings: latency code two (three clocks); wait active low; wait asserted during delay. figure 45. four-word burst read operation (with lb#/ub#) t ohz t olz high-z high-z t cbph don't care undefined legend: t cew high-z v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol a[22:0] adv# ce# lb#/ub# dq[15:0] wait t sp t csp t boe t sp t hd t hd v ih v il oe# we# t sp t hd t sp t hd read burst identified ( we# = high ) valid address t clk v ih v il clk t hd t hz valid output valid output valid output t khtl t koh t aclk high-z t khtl t khtl t khtl
144 cellularram type 2 cellram_00_a0 october 4, 2004 advance information ta b l e 4 1 . burst read timing parameters?4-word burst with lb#/ub# symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t aclk 911ns t boe 20 20 ns t cbph 55ns t cew 17.517.5ns t clk 12.5 15 ns t csp 45ns t hd 22ns t hz 88ns t khtl 911ns t khz 3838ns t klz 2525ns t koh 22ns t ohz 88ns t olz 55ns t sp 33ns
october 4, 2004 cellram_00_a0 cellularram type 2 145 advance information notes: 1. non-default bcr settings: latency code two (three clocks); wait active low; wait asserted during delay. 2. oe# can stay low during burst suspend. if oe# is low, dq[15:0] will continue to output valid data. figure 46. read burst suspend ta b l e 4 2 . burst read timing parameters?burst suspend symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t aclk 911ns t boe 20 20 ns t cbph 55ns t clk 12.5 15 ns t csp 45ns t hd 22ns t hz 88ns t koh 22ns t ohz 88ns t olz 55ns t ohz t olz high-z high-z t cbph don't care undefined legend: t cew high-z v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il a[22:0] adv# ce# lb#/ub# dq[15:0] wait t sp t csp t boe t sp t hd t hd v ih v il oe# we# t sp t hd t sp t hd t clk v ih v il clk t hz valid output valid output valid output valid output t koh t aclk (note 2) t boe t olz valid output valid output valid address t ohz valid address
146 cellularram type 2 cellram_00_a0 october 4, 2004 advance information t sp 33ns notes: 1. non-default bcr settings: latency code two (three clocks); wait active low; wait asserted during delay. 2. wait will assert lc + 1 or 2lc + 1 cycles for variable latency (depending upon refresh status). figure 47. continuous burst read showing an output delay with bcr[8] = 0 for end-of-row condition ta b l e 4 3 . burst read timing parameters?bcr[8] = 0 symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t aclk 911ns t clk 12.5 15 ns t khtl 911ns t koh 22ns table 42. burst read timing parameters?burst suspend (continued) symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t ohz don't care legend: v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol a[22:0] adv# ce# lb#/ub# wait v ih v il oe# we# t clk v ih v il clk (note 2) t khtl t khtl v oh v ol dq[15:0] t koh t aclk valid output valid output valid output valid output
october 4, 2004 cellram_00_a0 cellularram type 2 147 advance information figure 48. ce#-controlled asynchronous write table 44. asynchronous write timing parameters?ce#-controlled symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t as 00ns t aw 70 85 ns t bw 70 85 ns t cem 44s t dh t wp t dw t whz t bw t aa high-z high-z t lz don't care legend: valid address t hz t cew high-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il a[22:0] adv# ce# lb#/ub# oe# we# dq[15:0] in wait t as t aw t wr t cw t cem t wph v oh v ol dq[15:0] out valid input
148 cellularram type 2 cellram_00_a0 october 4, 2004 advance information t cew 17.517.5ns t cw 70 85 ns t dh 00ns t dw 23 23 ns t hz 88ns t lz 10 10 ns t wc 70 85 ns t whz 88ns t wp 46 55 ns t wph 10 10 ns t wr 00ns table 44. asynchronous write timing parameters?ce#-controlled (continued) symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax
october 4, 2004 cellram_00_a0 cellularram type 2 149 advance information figure 49. lb#/ub#-controlled asynchronous write ta b l e 4 5 . asynchronous write timing parameters?lb#/ub#-controlled symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t as 00ns t aw 70 85 ns t bw 70 85 ns t dh t wp t dw t whz t bw t wc high-z high-z t lz don't care legend: valid address t hz t cew high-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il a[22:0] adv# ce# lb#/ub# oe# we# dq[15:0] in wait t as t aw t wr t cw t cem t wph v oh v ol dq[15:0] out valid input
150 cellularram type 2 cellram_00_a0 october 4, 2004 advance information t cem 44s t cew 17.517.5ns t cw 70 85 ns t dh 00ns t dw 23 23 ns t hz 88ns t lz 10 10 ns t wc 70 85 ns t whz 88ns t wp 46 55 ns t wph 10 10 ns t wr 00ns table 45. asynchronous write timing parameters?lb#/ub#-controlled (continued) symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax
october 4, 2004 cellram_00_a0 cellularram type 2 151 advance information figure 50. we#-controlled asynchronous write ta b l e 4 6 . asynchronous write timing parameters?we#-controlled symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t as 00ns t dh t wp t dw t whz t bw t wc high-z high-z t lz don't care legend: valid address t hz t cew high-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il a[22:0] adv# ce# lb#/ub# oe# we# dq[15:0] in wait t aw t wr t cw t cem t wph v oh v ol dq[15:0] out valid input t ow t as
152 cellularram type 2 cellram_00_a0 october 4, 2004 advance information t aw 70 85 ns t bw 70 85 ns t cem 44s t cew 17.517.5ns t cw 70 85 ns t dh 00ns t dw 23 23 ns t hz 88ns t lz 10 10 ns t ow 55ns t wc 70 85 ns t whz 88ns t wp 46 55 ns t wph 10 10 ns t wr 00ns table 46. asynchronous write timing parameters?we#-controlled (continued) symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax
october 4, 2004 cellram_00_a0 cellularram type 2 153 advance information figure 51. asynchronous write using adv# t dh t wp t dw t whz t bw high-z high-z t lz don't care legend: t hz t cew high-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il a[22:0] adv# ce# lb#/ub# oe# we# dq[15:0] in wait t avs t cw t cem t wph v oh v ol dq[15:0] out valid input t ow t as valid address t aw t avh t vs t vp t vph t as
154 cellularram type 2 cellram_00_a0 october 4, 2004 advance information ta b l e 4 7 . asynchronous write timing parameters using adv# symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t as 00ns t avh 55ns t avs 10 10 ns t aw 70 85 ns t bw 70 85 ns t cem 44s t cew 17.517.5ns t cw 70 85 ns t dh 00ns t dw 23 23 ns t hz 88ns t lz 10 10 ns t ow 55ns t as 00ns t vp 10 10 ns t vph 10 10 ns t vs 70 85 ns t whz 88ns t wp 46 55 ns t wph 10 10 ns
october 4, 2004 cellram_00_a0 cellularram type 2 155 advance information notes: 1. non-default bcr settings: latency code two (three clocks); wait active low; wait asserted during delay; burst length four; burst wrap enabled. figure 52. burst write operation t ohz high-z don't care legend: t cew high-z v ih v il v ih v il v ih v il v oh v ol v ih v il a[22:0] adv# dq[15:0] wait t sp t sp t hd t hd v ih v il oe# we# t sp t hd v ih v il lb#/ub# t sp t hd read burst identified ( we# = low ) t clk t khkl t kp t kp v ih v il clk t hz t khtl t hd t sp valid address t cbph v ih v il ce# t csp t hd (note 2) d[1] d[2] d[3] d[0]
156 cellularram type 2 cellram_00_a0 october 4, 2004 advance information ta b l e 4 8 . burst write timing parameters symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t cbph 55ns t cew 17.517.5ns t clk 12.5 15 ns t csp 45ns t hd 22ns t hz 88ns t khkl 1.6 1.6 ns t khtl 911ns t kp 33ns t sp 33ns
october 4, 2004 cellram_00_a0 cellularram type 2 157 advance information notes: 1. non-default bcr settings: latency code two (three clocks); wait active low; wait asserted during delay. 2. wait will assert lc + 1 or 2lc + 1 cycles for variable latency (depending upon refresh status). figure 53. continuous burst write showing an output delay with bcr[8] = 0 for end-of-row condition ta b l e 4 9 . burst write timing parameters?bcr[8] = 0 symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t clk 12.5 15 ns t hd 22ns t khtl 811ns t sp 33ns don't care legend: v ih v il v ih v il v ih v il v ih v il v oh v ol a[22:0] adv# ce# lb#/ub# wait t clk v ih v il clk (note 2) v ih v il oe# t ohz v ih v il we# t khtl t khtl v oh v ol dq[15:0] t hd t sp valid input d[n] valid input d[n+1] valid input d[n+3] valid input d[n+2] end of row
158 cellularram type 2 cellram_00_a0 october 4, 2004 advance information notes: 1. non-default bcr settings: latency code two (three clocks); wait active low; wait asserted during delay. 2. to allow self-refresh operations to occur between transactions, ce# must remain high for at least 5ns (t cbph ) to schedule the appropriate internal refresh operation. ce# can stay low between burst read and burst write operations. see ?how extended timings impact cellularram? operation? for restrictions on the maximum ce# low time (t cem ). figure 54. burst write followed by burst read ta b l e 5 0 . write timing parameters?burst write followed by burst read symbol 70ns/80 mhz 85ns/66 mhz units min max min max t cbph 55ns t clk 12.5 20 15 20 ns t csp 4 20520ns t hd 22ns t sp 33ns ta b l e 5 1 . read timing parameters?burst write followed by burst read symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t aclk 911ns t boe 20 20 ns t clk 12.5 15 ns t ohz high-z high-z t cbph high-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol a[22:0] adv# ce# l b#/ub# d q[15:0] wait t sp t csp t sp t hd t hd v ih v il oe# we# t sp t hd t clk v ih v il clk t hd t boe valid address t sp t hd valid address t sp t hd (note 2) t csp t sp t hd t sp t hd d[0] d[3] d[2] d[1] valid output valid output valid output valid output v oh v ol t koh t aclk t sp t hd high-z don't care undefine d legend:
october 4, 2004 cellram_00_a0 cellularram type 2 159 advance information t csp 45ns t hd 22ns t koh 22ns t ohz 88ns t sp 33ns notes: 1. non-default bcr settings: latency code two (three clocks); wait active low; wait asserted during delay. 2. when transitioning between asynchronous and variable-latency burst operations, ce# must go high. if ce# goes high, it must remain high for at least 5ns (t cbph ) to schedule the appropriate internal refresh operation. see ?how extended timings impact cellularram? operation? for restrictions on the maximum ce# low time (t cem ). figure 55. asynchronous write followed by burst read table 51. read timing parameters?burst write followed by burst read (continued) symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t ohz high-z high-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol a[22:0] adv# ce# lb#/ub# dq[15:0] wait t csp t sp t hd v ih v il oe# we# t sp t hd t clk v ih v il clk t boe valid address t wc t wc (note 2) t wp t wph t sp t hd valid output valid output valid output valid output v oh v ol t koh t aclk high-z don't care undefined legend: valid address valid address t cka t sp t hd t bw t cw t aw t wr t cbph t wc t cew data t whz data t vph t avs t avh t vp t vs t cvs t as t dh t dw
160 cellularram type 2 cellram_00_a0 october 4, 2004 advance information ta b l e 5 2 . write timing parameters?asynchronous write followed by burst read symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t avh 55ns t as 00ns t avs 10 10 ns t aw 70 85 ns t bw 70 85 ns t cka 70 85 ns t cvs 10 10 ns t cw 70 85 ns t dh 00ns t dw 20 23 ns t vp 10 10 ns t vph 10 10 ns t vs 70 85 ns t wc 70 85 ns t whz 88ns t wp 46 55 ns t wph 10 10 ns t wr 00ns ta b l e 5 3 . read timing parameters?asynchronous write followed by burst read symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t aclk 911ns t boe 20 20 ns t cbph 55ns t cew 17.517.5ns t clk 12.5 15 ns t csp 45ns t hd 22ns t koh 22ns t ohz 88ns t sp 33ns
october 4, 2004 cellram_00_a0 cellularram type 2 161 advance information notes: 1. non-default bcr settings: latency code two (three clocks); wait active low; wait asserted during delay. 2. when transitioning between asynchronous and variable-latency burst operations, ce# must go high. if ce# goes high, it must remain high for at least 5ns (t cbph ) to schedule the appropriate internal refresh operation. see ?how extended timings impact cellularram? operation? for restrictions on the maximum ce# low time (t cem ). figure 56. asynchronous write (adv# low) followed by burst read ta b l e 5 4 . asynchronous write timing parameters?adv# low symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t aw 70 85 ns t bw 70 85 ns t cka 70 85 ns t cw 70 85 ns t dh 00ns t dw 23 23 ns t wc 70 85 ns t whz 88ns t ohz high-z high-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol a[22:0] adv# ce# lb#/ub# dq[15:0] wait t csp t sp t hd v ih v il oe# we# t sp t hd t clk v ih v il clk t boe valid address t wc t wc (note 2) t wp t wph t sp t hd valid output valid output valid output valid output v oh v ol t koh t aclk high-z don't care undefined legend: valid address valid address t cka t sp t hd t bw t cw t aw t wr t csp t wc t cew data t dh t whz data t dw
162 cellularram type 2 cellram_00_a0 october 4, 2004 advance information t wp 46 55 ns t wph 10 10 ns t wr 00ns table 55. burst read timing parameters symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t aclk 911ns t boe 20 20 ns t cbph 55ns t cew 17.517.5ns t clk 12.5 15 ns t csp 45ns t hd 22ns t koh 22ns t ohz 88ns t sp 33ns table 54. asynchronous write timing parameters?adv# low (continued) symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax
october 4, 2004 cellram_00_a0 cellularram type 2 163 advance information notes: 1. non-default bcr settings: latency code two (three clocks); wait active low; wait asserted during delay. 2. when transitioning between asynchronous and variable-latency burst operations, ce# must go high. if ce# goes high, it must remain high for at least 5ns (t cbph ) to schedule the appropriate internal refresh operation. see ?how extended timings impact cellularram? operation? for restrictions on the maximum ce# low time (t cem ). figure 57. burst read followed by asynchronous write (we#-controlled) valid address t sp t hd t ohz high-z high-z v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol a[22:0] adv# ce# dq[15:0] wait t hd t wc v ih v il oe# we# t clk v ih v il clk t sp t hd (note 2) t wp t wph t sp t hd valid output t cbph t koh t aclk don't care undefined legend: valid address v ih v il lb#/ub# t olz t aw t wr t csp t bw t dh t khtl t dw t sp t hd t hz t boe t cem t cw t as t cew t cew t hz read burst identified ( we# = high ) high-z valid input
164 cellularram type 2 cellram_00_a0 october 4, 2004 advance information ta b l e 5 6 . burst read timing parameters symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t aclk 911ns t boe 20 20 ns t cbph 55ns t cew 17.517.5ns t clk 12.5 15 ns t csp 45ns t hd 22ns t hz 88ns t khkl 1.6 1.6 ns t khtl 911ns t koh 22ns t kp 33ns t ohz 88ns ta b l e 5 7 . asynchronous write timing parameters?we# controlled symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t as 00ns t aw 70 85 ns t bw 70 85 ns t cem 44s t cw 70 85 ns t dh 00ns t dw 23 23 ns t hz 88ns t wc 70 85 ns t wp 46 55 ns t wph 10 10 ns t wr 00ns
october 4, 2004 cellram_00_a0 cellularram type 2 165 advance information notes: 1. non-default bcr settings: latency code two (three clocks); wait active low; wait asserted during delay. 2. when transitioning between asynchronous and variable-latency burst operations, ce# must go high. if ce# goes high, it must remain high for at least 5ns (t cbph ) to schedule the appropriate internal refresh operation. see ?how extended timings impact cellularram? operation? for restrictions on the maximum ce# low time (t cem ). figure 58. burst read followed by as ynchronous write using adv# valid address t sp t hd t ohz high-z high-z v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol a[22:0] adv# ce# dq[15:0] wait t hd v ih v il oe# we# t clk v ih v il clk t sp t hd (note 2) t wp t wph t sp t hd valid output valid input t cbph t koh t aclk don't care undefined legend: valid address t as v ih v il lb#/ub# t olz t avs t avh t csp t bw t dh t khtl t dw t sp t hd t hz t boe t cem t aw t cw t vs t vp t vph t as t cew t cew t hz read burst identified ( we# = high ) high-z
166 cellularram type 2 cellram_00_a0 october 4, 2004 advance information ta b l e 5 8 . burst read timing parameters symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t aclk 911ns t boe 20 20 ns t cbph 55ns t cew 17.517.5ns t clk 12.5 15 ns t csp 45ns t hd 22ns t hz 88ns t khkl 1.6 1.6 ns t khtl 911ns t koh 22ns t kp 33ns t ohz 88ns ta b l e 5 9 . asynchronous write timing parameters using adv# symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t as 00ns t avh 55ns t avs 10 10 ns t aw 70 85 ns t bw 70 85 ns t cem 44s t cew 17.517.5ns t cw 70 85 ns t dh 00ns t dw 23 23 ns t hz 88ns t vp 10 10 ns t vph 10 10 ns t vs 70 85 ns t wp 46 55 ns t wph 10 10 ns
october 4, 2004 cellram_00_a0 cellularram type 2 167 advance information t wr 00ns note: ce# can stay low when transitioning between asynchronous operations. if ce# goes high , it must remain h igh for at least 5ns (t cbph ) to schedule the appropriate internal refresh operation. see ?how extended timings impact cel- lularram? operation? for restrictions on the maximum ce# low time (t cem ). figure 59. asynchronous write followed by asynchronous read?adv# low ta b l e 6 0 . write timing parameters?adv# low symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t as 00ns t aw 70 85 ns t bw 70 85 ns t cw 70 85 ns table 59. asynchronous write timing parameters using adv# (continued) symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t ohz high-z high-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol a[22:0] adv# ce# lb#/ub# dq[15:0] wait t cem v ih v il oe# we# t blz t oe valid address (note) t wp t wph valid output v oh v ol t olz don't care undefined legend: valid address valid address t bw t cw t aw t wr t cbph t wc data t whz data t as t dh t dw t hz t hz t bhz t aa t hz t lz
168 cellularram type 2 cellram_00_a0 october 4, 2004 advance information t dh 00ns t dw 23 23 ns t hz 88ns t wc 70 85 ns t whz 88ns t wp 46 55 ns t wph 10 10 ns t wr 00ns ta b l e 6 1 . read timing parameters?adv# low symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t aa 70 85 ns t bhz 88ns t blz 10 10 ns t cbph 55ns t cem 44s t hz 88ns t lz 10 10 ns t oe 20 20 ns t ohz 88ns t olz 55ns table 60. write timing parameters?adv# low (continued) symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax
october 4, 2004 cellram_00_a0 cellularram type 2 169 advance information note: ce# can stay low when transitioning between asynchronous operations. if ce# goes high , it must remain h igh for at least 5ns (t cbph ) to schedule the appropriate internal refresh operation. see ?how extended timings impact cel- lularram? operation? for restrictions on the maximum ce# low time (t cem ). figure 60. asynchronous write followed by asynchronous read ta b l e 6 2 . write timing parameters?asynchronous write followed by asynchronous read symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t as 00ns t avh 55ns t avs 10 10 ns t aw 70 85 ns t bw 70 85 ns t cvs 10 10 ns t cw 70 85 ns t dh 00ns t dw 23 23 ns t ohz high-z high-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol a[22:0] adv# ce# lb#/ub# dq[15:0] wait t cem v ih v il oe# we# t blz t olz valid address (note) t wp t wph valid output v oh v ol t oe don't care undefined legend: valid address valid address t bw t cw t aw t wr t cbph t wc data t whz data t as t dh t dw t bhz t aa t hz t lz t avs t avh t vph t vp t vs t cvs t as
170 cellularram type 2 cellram_00_a0 october 4, 2004 advance information how extended timings impact cellularram? operation introduction this section describes cellularram? timing requirements in systems that per- form extended operations. cellularram products use a dram technology that periodically requires refresh to ensure against data corruption. cellularram devices include on-chip circuitry that performs the required refresh in a manner that is completely transparent in sys- tems with normal bus timings. the re fresh circuitry imposes constraints on timings in systems that take longer than 4s to complete an operation. write operations are affected if the device is configured for asynchronous operation. both read and write operations are affected if the device is configured for page or burst-mode operation. t vp 10 10 ns t vph 10 10 ns t vs 70 85 ns t wc 70 85 ns t whz 88ns t wp 46 55 ns t wph 10 10 ns t wr 00ns ta b l e 6 3 . read timing parameters?asynchronous write followed by asynchronous read symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax t aa 70 85 ns t bhz 88ns t blz 10 10 ns t cbph 55ns t cem 44s t hz 88ns t lz 10 10 ns t oe 20 20 ns t ohz 88ns t olz 55ns table 62. write timing parameters?asynchronous write followed by asynchronous read symbol 70ns/80 mhz 85ns/66 mhz units minmaxminmax
october 4, 2004 cellram_00_a0 cellularram type 2 171 advance information asynchronous write operation the timing parameters provided in figure 33 require that all write operations must be completed within 4s. after completing a write operation, the device must either enter standby (by transitioning ce# high), or else perform a second operation (read or write) using a new address. figure 61 and figure 62 dem- onstrate these constraints as they apply during an asynchronous (page-mode- disabled) operation. either the ce# active period (t cem in figure 61 ) or the ad- dress valid period (t tm in figure 62 ) must be less than 4s during any write operation, otherwise, the extended write timings must be used. extended write timing? asynchronous write operation modified timings are required during extended write operations (see figure 63 ). an extended write operation requires that both the write pulse width (t wp ) and the data valid period (t dw ) be lengthened to at least the minimum write cycle time (t wc [min]). these increased timings ensure that time is available for both a refresh operation and a successful completion of the write operation. figure 61. extended timing for t cem figure 62. extended timing for t tm ta b l e 6 4 . extended cycle impact on read and write cycles page mode timing constraint read cycle write cycle asynchronous page mode disabled t cem and t tm > 4s (see figure 61 and figure 62 .) no impact. must use extended write timing. (see figure 62 ) asynchronous page mode enabled t cem > 4s (see figure 61 .) all following intrapage read access times are t aa (not t apa ). must use extended write timing. (see figure 63 ) burst t cem > 4s (see figure 61 .) burst must cross a row boundary within 4s. ce# address t cem 4s < ce# address tm < t 4s
172 cellularram type 2 cellram_00_a0 october 4, 2004 advance information page mode read operation when a cellularram device is configured for page mode operation, the address inputs are used to accelerate read accesses and cannot be used by the on-chip circuitry to schedule refresh. if ce# is low longer than the t cem maximum time of 4s during a read operation, the system must allow t aa (not t apa , as would otherwise be expected) for all subsequent intrapage accesses until ce# goes high. burst-mode operation when configured for burst-mode operation, it is necessary to allow the device to perform a refresh within any 4s window. one of two conditions will enable the device to schedule a refresh within 4s. the first condition is when all burst op- erations complete within 4s. a burst completes when the ce# signal is registered high on a rising clock edge. the second condition that allows a refresh is when a burst access crosses a row boundary. the row-boundary crossing causes wait to be asserted while the next row is accessed and enables the scheduling of refresh. summary cellularram products are designed to ensure that any possible asynchronous tim- ings do not cause data corruption due to lack of refresh. slow bus timings on asynchronous write operations require that t wp and t dw be lengthened. slow bus timings during asynchronous page read operations cause the next intrapage read data to be delayed to t aa . burst mode timings must allow the device to perform a refresh within any 4s period. a burst operation must either complete (ce# registered high) or cross a row boundary within 4s to ensure successful refresh scheduling. these timing requirements are likely to have little or no impact when interfacing a cellularram device with a low-speed memory bus. figure 63. extended write operation t cem or t tm > 4 s t wp > t wc (min) t dw > t wc (min) address ce# lb#/ub# we# data-in
december 15, 2004 cellram_02_a0 cellularram-2a 173 advance information cellularram-2a 64 megabit asynchronous cellularram features ? asynchronous and page mode interface ? random access time: 70 ns ? page mode read access ? sixteen-word page size ? interpage read access: 70 ns ? intrapage read access: 20 ns ? v cc , v ccq voltages ? 1.70 v to 1.95 v v cc ? 1.70 v to 2.25 v v ccq ? low power consumption ? asynchronous read < 25 ma ? intrapage read < 15 ma ? standby: 100 a ? deep power-down < 10 a ? low-power features ? temperature compensated refresh (tcr) ? partial array refresh (par) ? deep power-down (dpd) mode general description cellularram? products are high-speed, cmos dynamic random access memories that have been developed for low-power portable applications. the 64mb device is organized as 4 meg x 16 bits. these devices include the industry-standard, asynchronous memory interface found on other low-power sram or pseudo sram offerings. a user-accessible configuration register (cr) has been included to define device operation. the cr defines how the cellul arram device performs on-chip refresh and whether page mode read accesses are permitted. this register is automati- cally loaded with a default setting during power-up and can be updated at any time during normal operation. to operate smoothly on an asynchronous memory bus, cellularram products have incorporated a transparent self refresh mechanism. the hidden refresh re- quires no additional support from the system memory controller and has no significant impact on device read/write performance. special attention has been focused on current consumption during self refresh. cellularram products include three system-accessible mechanisms used to min- imize refresh current. temperature compensated refresh (tcr) is used to adjust the refresh rate according to the case temperature. the refresh rate can be de- creased at lower temperatures to minimize current consumption during standby. setting the sleep enable pin zz# to low enables one of two low-power modes: partial array refresh (par); or deep power-down (dpd). par limits refresh to only that part of the dram array that contains essential data. dpd halts refresh oper-
174 cellularram-2a cellram_02_a0 december 15, 2004 advance information ation altogether and is used when no vital information is stored in the device. these three refresh mechanisms are accessed through the cr. note: functional block diagrams illustrate simplified device operation. see truth table, pin descriptions, and timing di- agrams for detailed information. figure 64. functional block diagram ta b l e 6 5 . pin descriptions symbol type description a[21:0] input address inputs: inputs for the address acce ssed during read or write operations. the address lines are also used to define the value to be loaded into the configuration register. zz# input sleep enable: when zz# is low, the configuration register can be loaded or the device can enter one of two low-power modes (dpd or par). ce# input chip enable: activates the device when low. when ce# is high, the device is disabled and goes into standby power mode. oe# input output enable: enables the output buffers when low. when oe# is high, the output buffers are disabled. we# input write enable: enables write operations when low. lb# input lower byte enable. dq[7:0] ub# input upper byte enable. dq[15:8] dq[15:0] input/ output data inputs/outputs. v cc supply device power supply: (1.7 v?1.95 v) power supply for device core operation. v cc q supply i/o power supply: (1.8 v) power supply for input/output buffers. v ss supply v ss must be connected to ground. a[21:0] input/ output mux and buffers control logic 4,096k x 16 dram memory array ce# we# oe# lb# ub# dq[7:0] dq[15:8] address decode logic configuration register (cr) zz#
december 15, 2004 cellram_02_a0 cellularram-2a 175 advance information notes: 1. when lb# and ub# are in select mode (low), dq[15:0] are affected. when lb# only is in select mode, only dq[7:0] are affected. when ub# only is in the select mode, dq[15:8] are affected. 2. when the device is in standby mode, control inputs (we#, oe#), address inputs, and data inputs/outputs are internally isolated from any external influence. 3. when we# is invoked, the oe# input is internally disabled and has no effect on the i/os. 4. the device consumes active power in this mode whenever addresses are changed. 5. v in = v cc or 0v; all device balls must be static (unswitched) in order to achieve minimum standby current. 6. dpd is enabled when configuration register bit cr[4] is ?0?; otherwise, par is enabled. v ss q supply v ss q must be connected to ground. table 66. bus operations?asynchronous mode mode power ce# we# oe# lb#/ub# zz# dq[15:0] ( note 1 )notes standby standby h x x x h high-z 2 , 5 read active > standby l h l l h data-out 1 , 4 write active > standby l l x l h data-in 1 , 3 , 4 active standby l h h l h high-z 4 , 5 par partial array refresh h x x x l high-z 6 dpd deep power-down h x x x l high-z 6 load configuration register active l l x x l high-z table 65. pin descriptions (continued) symbol type description
176 cellularram-2a cellram_02_a0 december 15, 2004 advance information functional description the 64mb async/page cellularram device is a high-density alternative to sram and pseudo sram products, popular in low-power, portable applications. the de- vice contains 67,108,864 bits organized as 4,194,304 addresses by 16 bits. it includes the industry-standard, asynchronous memory interface found on other low-power sram or pseudo sram offerings. page mode accesses are also in- cluded as a bandwidth-enhancing extension to the asynchronous read protocol. power-up initialization cellularram products include an on-chip voltage sensor that is used to launch the power-up initialization process. initialization will load the cr with its default set- tings. v cc and v ccq must be applied simultaneously, and when they reach a stable level above 1.70 v, the device requires 150 s to complete its self initial- ization process (see figure 2). during the initialization period, ce# should remain high. when initialization is complete, the device is ready for normal operation. at power-up, the cr is set to 0070h. bus operating modes cellularram products incorporate the industry-standard, asynchronous interface found on other low-power sram or pseudo sram offerings. this bus interface supports asynchronous read and write operations as well as the bandwidth- enhancing page mode read operation. the specific interface that is supported is defined by the value loaded into the cr. asynchronous mode cellularram products power up in the asynchronous operating mode. this mode uses the industry standard sram control interface (ce#, oe#, we#, lb#/ ub#). read operations ( figure 66 ) are initiated by bringing ce#, oe#, and lb#/ub# low while keeping we# high. valid data will be driven out of the i/os after the specified access time has elapsed. write operations ( figure 67 ) occur when ce#, we#, and lb#/ ub# are driven low. during write operations, the level of oe# is a ?don't care?; we# will override oe#. the data to be written will be latched on the rising edge of ce#, we#, or lb#/ub# (whichever occurs first). figure 65. power-up initialization timing v cc v cc q t pu > 150 s device initialization device ready for normal operation v cc = 1.7 v
december 15, 2004 cellram_02_a0 cellularram-2a 177 advance information page mode read operation page mode is a performance-enhancing extension to the legacy asynchronous read operation. in page mode-capable products, an initial asynchronous read access is performed, then adjacent addresses can be quickly read by simply changing the low-order address. addresses a[3:0] are used to determine the members of the 16-address cellularram page. addresses a[4] and higher must remain fixed during the entire page mode access. figure 68 shows the timing di- agram for a page mode access. figure 66. read operation figure 67. write operation data valid address valid t rc = read cycle time ce# oe# we# address data lb#/ub# don't care data valid address valid t wc = write cycle time ce# oe# we# address data lb#/ub# don't care
178 cellularram-2a cellram_02_a0 december 15, 2004 advance information page mode takes advantage of the fact that adjacent addresses can be read in a shorter period of time than random addresses. write operations do not include comparable page mode functionality. lb# / ub# operation the lower byte (lb#) enable and upper byte (ub#) enable signals allow for byte- wide data transfers. during read operat ions, enabled bytes are driven onto the dqs. the dqs associated with a disabled byte are put into a high-z state during a read operation. during write operations, any disabled bytes will not be trans- ferred to the memory array and the internal value will remain unchanged. during a write cycle, the data to be written is latched on the rising edge of ce#, we#, lb#, or ub#, whichever occurs first. when both the lb# and ub# are disabled (h igh) during an operation, the device will disable the data bus from receiving or transmitting data. although the device will seem to be deselected, the device remains in an active mode as long as ce# remains low. low power operation standby mode operation during standby, the device current consumption is reduced to the level necessary to perform the dram refresh operation on the full array. standby operation oc- curs when ce# and zz# are high and there are no transactions in progress. the device will enter standby operation during read and write operations where the address and control inputs remain static for an extended period of time. this ?active? standby mode will continue until a change occurs to the ad- dress or control inputs. temperature compensated refresh temperature compensated refresh (tcr) is used to adjust the refresh rate de- pending on the device operating temperature. dram technology requires more figure 68. page mode read operation ce# oe# we# address data lb#/ub# don't care add[1] add[2] add[3] t aa d[0] t apa d[1] t apa d[2] t apa d[3] add[0]
december 15, 2004 cellram_02_a0 cellularram-2a 179 advance information frequent refresh operations to maintain data integrity as temperatures increase. more frequent refresh is required due to the increased leakage of the dram's ca- pacitive storage elements as temperatures rise. a decreased refresh rate at lower temperatures will facilitate a savings in standby current. tcr allows for adequate refresh at four different temperature thresholds: +15c, +45c, +70c, and +85c. the setting selected must be for a temperature higher than the case temperature of the cellularram device. if the case temper- ature is +50c, the system can minimize self refresh current consumption by selecting the +70c setting. the +15c and +45c settings would result in inad- equate refreshing and cause data corruption. partial array refresh partial array refresh (par) restricts refresh operation to a portion of the total memory array. this feature enables the system to reduce refresh current by only refreshing that part of the memory array that is absolutely necessary. the refresh options are full array, three-quarters arra y, one-half array, one-quarter a rray, or none of the array. data stored in addresses not receiving refresh will become cor- rupted. the mapping of these partitions can start at either the beginning or the end of the address map (tables 5 and 6). read and write operations are ignored during par operation. the device can only enter par mode if the sleep bit in the configuration register has been set high (cr[4] = 1). par is initiated by bring the zz# pin to the low state for longer than 10s. returning zz# to high will cause an exit from par and the entire array will be immediately available for read and write operations. deep power-down operation deep power-down (dpd) operation disables all refresh-related activity. this mode is used when the system does not require the storage provided by the cellular- ram device. any stored data will become corrupted when dpd is entered. when refresh activity has been re-enabled, the cellularram device will require 150s to perform an initialization procedure before normal operations can resume. read and write operations are ignored during dpd operation. the device can only enter dpd if the sleep bit in the cr has been set low (cr[4] = 0). dpd is initiated by bringing the zz# pin to the low state for longer than 10s. returning zz# to high will cause the device to exit dpd and begin a 150s initialization process. during this 150s period, the current consumption will be higher than the specified standby levels but considerably lower than the active current specification. driving the zz# pin low will place the device in the par mode if the sleep bit in the cr has been set high (cr[4] = 1). configuration register operation the configuration register (cr) defines how the cellularram device performs its transparent self refresh. this register is automatically loaded with default settings during power-up and can be updated anytime while the device is operating in a standby state. the cr is loaded using a write operation immediately after zz# makes a high- to-low transition ( figure 69 ). the values placed on addresses a[21:0] are latched into the cr on the rising edge of ce# or we#, whichever occurs first. al-
180 cellularram-2a cellram_02_a0 december 15, 2004 advance information tering the refresh parameters can dramatically reduce current consumption during standby mode. page mode control is also embedded into the configuration register. ta b l e 6 7 describes the control bits used in the cr. at power up, the cr is set to 0070h. figure 69. load configuration register operation partial array refresh (cr[2:0]) default = full array refresh the par bits restrict refresh operation to a portion of the total memory array. this feature allows the system to reduce current by only refreshing that part of the memory array required by the host system. the refresh options are full array, three-quarters array, one-half array, one-quarter array, or none of the array. the mapping of these partitions can start at either the beginning or the end of the address map (see ta b l e 6 8 on page 181 ). sleep mode (cr[4]) default = par enabled, dpd disabled the sleep mode bit determines which low-power mode is to be entered when zz# is driven low. if cr[4] = 1, par operation is enabled. if cr[4] = 0, dpd opera- tion is enabled. dpd operation disables all refresh-related activity. this mode will be used when the system does not require the storage provided by the cellularram device. any stored data will become corrupted when dpd is enabled. when refresh activity has been re-enabled, the cellularram device will require 150s to perform an ini- tialization procedure before normal operation can resume. temperature compensated refresh (c r[6:5]) default = +85c operation the tcr bits allow for adequate refresh at four different temperature thresholds: +15c, +45c, +70c, and +85c. the setting selected must be for a tempera- ture higher than the case temperature of the cellularram device. if the case temperature is +50c, the system can minimize self refresh current consumption by selecting the +70c setting. the +15c and +45c settings would result in inadequate refreshing and cause data corruption. page mode read operation (cr[7]) default = disabled the page mode operation bit determines whether page mode read operations are enabled. in the power-up default state, page mode is disabled. address valid ce# zz# we# t < 500ns address
december 15, 2004 cellram_02_a0 cellularram-2a 181 advance information ta b l e 6 7 . configuration register bit mapping ta b l e 6 8 . 64mb address patterns for par (cr[4] = 1) cr[2] cr[1] cr[0] active section address space size density 0 0 0 full die 000000h?3fffffh 4 meg x 16 64mb 0 0 1 three-quarters of die 000000h?2fffffh 3 meg x 16 48mb 0 1 0 one-half of die 000000h?1fffffh 2 meg x 16 32mb 0 1 1 one-quarter of die 000000h?0fffffh 1 meg x 16 16mb 1 0 0 none of die 0 0 meg x 16 0mb 1 0 1 three-quarters of die 100000h?3fffffh 3 meg x 16 48mb 1 1 0 one-half of die 200000h?3fffffh 2 meg x 16 32mb 1 1 1 one-quarter of die 300000h?3fffffh 1 meg x 16 16mb par a4 a3 a2 a1 a0 configuration register address bus 4 1 2 3 0 reserved 6 5 a5 0 1 sleep mode dpd enabled par enabled (default) cr[4] tcr cr[6] cr[5] 11 1 1 00 0 0 maximum case temp. +85 c (default) +70 c +45 c +15 c a6 21? 8 reserved a[21:8] cr[1] 0 0 1 1 cr[0] 0 1 0 1 par refresh coverage full array (default) bottom 3/4 array bottom 1/2 array bottom 1/4 array cr[2] 0 0 0 0 00 1 01 1 1 0 1 11 1 none of array top 3/4 array top 1/2 array top 1/4 array sleep must be set to "0" all must be set to "0" a7 7 page 0 1 page mode enable/disable page mode disabled (default) page mode enabled cr[7]
182 cellularram-2a cellram_02_a0 december 15, 2004 advance information absolute maximum ratings voltage to any ball except v cc , v cc q relative to v ss . . . -0.50 v to (4.0 v or v cc q + 0.3 v, whichever is less) voltage on v cc supply relative to v ss . . . . . . . . . . . . . . . -0.20 v to +2.45 v voltage on v cc q supply relative to v ss . . . . . . . . . . . . . . . -0.20 v to +4.0 v storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oc to +150oc operating temperature (case) wireless. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25oc to +85oc industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oc to +85oc soldering temperature and time 10s (lead only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260oc *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating con- ditions for extended periods may affect reliability.
december 15, 2004 cellram_02_a0 cellularram-2a 183 advance information dc characteristics wireless temperature (-25c t c +85c) industrial temperature (-40c < t c < +85c) notes: 1. this parameter is specified with the outputs disabled to avoid external loading effects. the user must add current required to drive output capacitanc e expected in the actual system. 2. this device assumes a standby mode if the chip is disabled (ce# high). it will also automatically go into a standby mode whenever all input signals are quiescent (not toggling), regardless of the state of ce#, lb#, and ub#. in order to achieve low standby current, all inputs must be either vccq or vss. 3. isb (max) values measured with par set to full array and tcr set to +85c. notes: 1. itcr (max) values measured with full array refresh. 2. this device assumes a standby mode if the chip is disabled (ce# high). it will also automatically go into a standby mode whenever all input signals are quiescent (not toggling), regardless of the state of ce#, lb#, and ub#. in order to achieve low standby current, all inputs must be either vccq or vss. ta b l e 6 9 . electrical characteristics and operating conditions description conditions symbol min max units notes supply voltage v cc 1.70 1.95 v i/o supply voltage 1.8 v v ccq 1.70 2.25 v input high voltage v ih 1.4 v cc q + 0.2 v input low voltage v il -0.20 0.4 v output high voltage i oh = -0.2ma v oh 0.80 v ccq v output low voltage i ol = +0.2ma v ol 0.20 v ccq v input leakage current v in = 0 to v ccq i li 1a output leakage current oe# = v ih or chip disabled i lo 1a 2 read operating current v in = v ccq or 0v chip enabled, i out = 0 i cc1 25 ma 1 , 2 write operating current v in = v ccq or 0v chip enabled i cc2 25 ma 1 , 2 max standby current v in = v ccq or 0v chip disabled i sb 100 a 2 , 3 ta b l e 7 0 . temperature compensated refresh specifications and conditions description conditions symbol density max case temperature typ max units temperature compensated refresh standby current v in = v cc q or 0v, chip disabled i tcr 64 mb +85c 100 a +70c tbd +45c tbd +15c 50
184 cellularram-2a cellram_02_a0 december 15, 2004 advance information ta b l e 7 1 . partial array refresh specifications and conditions note:i par (max) values measured with tcr set to 85c. notes: 1. these parameters are verified in device characterization and are not 100% tested. ac characteristics description conditions symbol density array partition typ max units partially array refresh current v in = v cc q or 0v, zz# = low cr[4] = 1 i par 64 mb full 100 a 3/4 tbd 1/2 tbd 1/4 tbd 050 ta b l e 7 2 . deep power-down specifications description conditions symbol typ max units deep power-down v in = v cc q or 0v; +25c; zz# = low cr[4] = 0 i zz 10 a ta b l e 7 3 . capacitance specifications and conditions description conditions symbol min max units notes input capacitance t c = +25oc; f = 1 mhz; v in = 0v c in -6pf 1 input/output capacitance (dq) c io -6pf 1 notes: 1. ac test inputs are driven at vccq for a logic 1 and vss for a logic 0. input timing begins at vccq/2, and output timing ends at vccq/2. input rise and fall times (10% to 90%) < 1.6ns. figure 70. ac input/output reference waveform note: all tests are performed with the outputs configured for full drive strength (bcr[5] = 0). figure 71. output load circuit ta b l e 7 4 . output load circuit v cc qr1/r2 1.8 v 2.7 k ? output test points input v cc q v ss v cc q /2 v cc q/2 dut v cc q r1 r2 30pf test point
december 15, 2004 cellram_02_a0 cellularram-2a 185 advance information notes: 1. high-z to low-z timings are tested with the circuit shown in figure 71 on page 184 . the low-z timings measure a 100mv transition away from the high-z (v ccq /2) level toward either v oh or v ol . 2. low-z to high-z timings are tested with the circuit shown in figure 71 on page 184 . the high-z timings measure a 100mv transition from either v oh or v ol toward v ccq /2. ta b l e 7 5 . read cycle timing requirements parameter symbol min max units notes address access time t aa 70 ns page access time t apa 20 ns lb#/ub# access time t ba 70 ns lb#/ub# disable to high-z output t bhz 08ns 2 lb#/ub# enable to low-z output t blz 10 ns 1 chip select access time t co 70 ns chip disable to high-z output t hz 08ns 2 chip enable to low-z output t lz 10 ns 1 output enable to valid output t oe 20 ns output hold from address change t oh 5ns output disable to high-z output t ohz 08ns 2 output enable to low-z output t olz 5ns 1 page cycle time t pc 20 ns read cycle time t rc 70 ns
186 cellularram-2a cellram_02_a0 december 15, 2004 advance information notes: 1. high-z to low-z timings are tested with the circuit shown in figure 71 on page 184 . the low-z timings measure a 100mv transition away from the high-z (v ccq /2) level toward either v oh or v ol . 2. low-z to high-z timings are tested with the circuit shown in figure 71 on page 184 . the high-z timings measure a 100mv transition from either v oh or v ol toward v ccq /2. ta b l e 7 6 . write cycle timing requirements parameter symbol min max units notes address setup time t as 0ns address valid to end of write t aw 70 ns byte select to end of write t bw 70 ns ce# high time during write t ceh 5ns maximum ce# pulse width t cem 10 s chip enable to end of write t cw 70 ns data hold from write time t dh 0ns data write setup time t dw 23 ns chip enable to low-z output t lz 10 ns 1 end write to low-z output t ow 5ns write cycle time t wc 70 ns write to high-z output t whz 08ns 2 write pulse width t wp 46 write recovery time t wr 0ns table 77. load configuration register timing requirements parameter symbol min max units notes address setup time t as 0ns address valid to end of write t aw 70 ns chip deselect to zz# low t cdzz 5ns chip enable to end of write t cw 70 ns write cycle time t wc 70 ns write pulse width t wp 40 ns write recovery time t wr 0ns zz# low to we# low t zzwe 10 ns ta b l e 7 8 . deep power down timing requirements parameter symbol min max units notes chip deselect to zz# low t cdzz 5ns deep power-down recovery t r 150 s minimum zz# pulse width t zzmin 10 s
december 15, 2004 cellram_02_a0 cellularram-2a 187 advance information figure 73. load configuration register timing ta b l e 7 9 . power-up initialization timing parameters parameter symbol min max units notes initialization period (required before normal operations) t pu 150 s figure 72. power-up initialization period ta b l e 8 0 . load configuration register timing requirements symbol min max units symbol min max units t as 0 ns t wc 70 ns t aw 70 t wp 40 t cdzz 5t wr 0 t cw 70 t zzwe 10 500 t pu v cc , v cc q = 1.7v v cc (min) device ready fo r normal operation address zz# t wc t aw t wr t as ce# lb#/ub# t zzwe don?t car e we# t wp t cdzz opcode t cw oe#
188 cellularram-2a cellram_02_a0 december 15, 2004 advance information figure 75. single read operation (we# = v ih ) figure 74. deep power down entry/exit timing ta b l e 8 1 . load configuration register timing requirements symbol min max units t cdzz 5ns t r 150 s t zz(min) 10 s zz # ce# t zz (min) don?t car e t cdzz t r device ready for normal operatio n address oe# t rc t aa data-out ce# lb#/ub# t olz t lz don?t care undefined high-z data valid t ohz t ba t bhz t hz t blz t co t oe high-z address valid
december 15, 2004 cellram_02_a0 cellularram-2a 189 advance information figure 76. page mode read operation (we# = v ih ) ta b l e 8 2 . read timing parameters symbol min max units symbol min max units t aa 70 ns t lz 10 ns t ba 70 t oe 20 t bhz 08 t ohz 08 t blz 10 t olz 5 t co 70 t rc 70 t hz 08 ta b l e 8 3 . page mode read timing parameters symbol min max units symbol min max units t aa 70 ns t lz 10 ns t apa 20 t oe 20 t ba 70 t oh 5 t bhz 08 t ohz 08 t blz 10 t olz 5 t co 70 t pc 20 t hz 08 t rc 70 address a[21:4] oe# t aa data-out ce# lb#/ub# t olz t lz don?t care undefined high-z data valid t ohz t ba t bhz t hz t blz t co address a[3:0] data valid data valid data valid t rc t oh high-z t pc address valid t apa t oe
190 cellularram-2a cellram_02_a0 december 15, 2004 advance information figure 77. write cycle (we# control) ta b l e 8 4 . write timing parameters symbol min max units symbol min max units t as 0 ns t dw 23 ns t aw 70 t ow 5 t bw 70 t wc 70 t cem 10 s t whz 08 t cw 70 ns t wp 46 t dh 0t wr 0 address we# t wc t aw t wr data-in ce# lb#/ub# t bw t whz t ow t dh t dw t as t wp don?t car e high-z data-out data valid t cw t cem oe# address valid
december 15, 2004 cellram_02_a0 cellularram-2a 191 advance information figure 78. write timing parameters (ce# control) ta b l e 8 5 . write timing parameters (ce# control) symbol min max units symbol min max units t as 0 ns t dw 23 ns t aw 70 t lz 10 t bw 70 t wc 70 t ceh 5t whz 08 t cem 10 s t wp 46 t cw 70 ns t wr 0 t dh 0 address we# t wc t aw t cw t cem t wr t ceh data-in ce# lb#/ub# t bw t whz t lz t as t dh t dw t wp don't care high-z data-out data valid oe#
192 cellularram-2a cellram_02_a0 december 15, 2004 advance information figure 79. write cycle (lb# / ub# control) ta b l e 8 6 . write timing parameters (lb# / ub# control) symbol min max units symbol min max units t as 0 ns t dw 23 ns t aw 70 t lz 10 t bw 70 t wc 70 t cem 10 s t whz 08 t dh 0ns t wr 0 address we# t wc t aw t wr data-in ce# lb#/ub# t bw t whz t dh t as t dw t lz don?t care data-out data valid t cem oe# high-z
december 15, 2004 cellram_02_a0 cellularram-2a 193 advance information how extended timings impact cellularram? operation introduction cellularram products use a dram technology that periodically requires refresh to ensure against data corruption. cellularram devices include on-chip circuitry that performs the required refresh in a manner that is completely transparent in sys- tems with normal bus timings. the refresh circuitry does impose constraints on timings in systems that take longer th an 10s to complete write operations. this section describes cellularram timing requirements in systems that perform extended operations. operation when page mode is disabled cellularram products require that all write operations must be completed within 10s. after completing an operation, the device must either enter standby (by transitioning ce# high), or else perf orm a second operation using a new ad- dress. figures 80 and 81 demonstrate these constraints as they apply during an asynchronous (page-mode-disabled) operation. either the ce# active period (t cem in figure 80 ) or the address valid period (t tm in figure 81 ) must be less than 10 s during any operation to accommodate orderly scheduling of refresh. note:timing constraints when page mode is enabled. figure 80. extended timing for t cem note:timing constraints when page mode is enabled. figure 81. extended timing for t tm operation when page mode is enabled when a cellularram device is configured for page mode operation, the address inputs are used to accelerate read accesses and cannot be used by the on-chip circuitry to schedule refresh. ce# must return high upon completion of all write operations when page mode is enabled ( figure 82 ). the total time taken for a write operation should not exceed 10 s to accommodate orderly sched- uling of refresh. ce# address t cem 10 s < ce# address tm < t 10s
194 cellularram-2a cellram_02_a0 december 15, 2004 advance information note:timing constraints when page mode is enabled. figure 82. extended timing for t cem (2) impact on extended write operations modified timings are only required during extended write operations (see figure 83 below). an extended write operation requires that both the write pulse width (t wp ) and the data valid period (t dw ) will need to be lengthened to at least the minimum write cycle time (t wc[min] ). these increased timings ensure that time is available for both a refresh operation and successful completion of the write operation. summary cellularram products are designed to ensure that any possible bus timings do not cause corruption of array data due to lack of refresh. the on-chip refresh circuitry will only affect the required timings for write operations (reads are unaffected) performed in a system with a slow memory interface. the impact for write op- erations is that some of the timing parameters (t wp , t dw ) are lengthened. the modified timings are likely to have little or no impact when interfacing a cellular- ram device with a low-speed memory bus. figure 83. extended write operation c e# t cem 10s < t cem or t tm > 4 s t wp > t wc (min) t dw > t wc (min) address ce# lb#/ub# we# data-in
december 17, 2004 S71GS256/128n_00_a0 revision summary 195 advance information revision summary revision a0 (december 17, 2004) initial release. colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contem plated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and c ould lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerabl e (i.e., submersible repeater and artificial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages ari sing in connection with above-men- tioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, dam age or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain re strictions on export under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any oth er country, the prior au- thorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the information in this docu ment is provided as is with- out warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantab ility, non-infringement of third- party rights, or any other warranty, express, implied, or statutory. spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2004 spansion. all rights reserved. spansion, the spansion logo, mirrorbit, combinations thereof, and expressflash are trademarks of spansion. other company and product names used in this publication are for identification purposes only and may be trademarks of their re spective companies.

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